公开(公告)号：US11956972B2

公开(公告)日：2024-04-09

申请号：US17228720

申请日：2021-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Po-Kai Hsu

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.

公开(公告)号：US20240111220A1

公开(公告)日：2024-04-04

申请号：US17979765

申请日：2022-11-03

Applicant: United Microelectronics Corp.

Inventor： Yu-Wei Cheng

IPC: G03F7/20

CPC classification number: G03F7/70633

Abstract: An overlay target that includes a plurality of working zones and a plurality of line segments. The line segments in each of the working zones have a plurality of widths and are parallel to each other.

公开(公告)号：US11950513B2

公开(公告)日：2024-04-02

申请号：US17857185

申请日：2022-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Wei Chen ,  Po-Kai Hsu ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H10N50/01 ,  H01F10/32 ,  H10N50/80

CPC classification number: H10N50/01 ,  H01F10/3254 ,  H01F10/329 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

公开(公告)号：US11950431B2

公开(公告)日：2024-04-02

申请号：US18073574

申请日：2022-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Chen ,  Hui-Lin Wang ,  Yu-Ru Yang ,  Chin-Fu Lin ,  Yi-Syun Chou ,  Chun-Yao Yang

IPC: H01L27/14 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L23/552 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/34 ,  H01L23/552 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

公开(公告)号：US20240107902A1

公开(公告)日：2024-03-28

申请号：US17970560

申请日：2022-10-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

IPC: H01L45/00 ,  H01L23/48 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L23/481 ,  H01L27/24 ,  H01L45/1666

Abstract: A resistive memory device includes a dielectric layer, a via connection structure, a stacked structure, and an insulating structure. The via connection structure is disposed in the dielectric layer. The stacked structure is disposed on the via connection structure and the dielectric layer. The insulating structure penetrates through the stacked structure in a vertical direction and divides the stacked structure into a first memory cell unit and a second memory cell unit. The first memory cell unit includes a first bottom electrode, and the second memory cell unit includes a second bottom electrode separated from the first bottom electrode by the insulating structure. The via connection structure is electrically connected with the first bottom electrode and the second bottom electrode.

公开(公告)号：US20240103383A1

公开(公告)日：2024-03-28

申请号：US17961575

申请日：2022-10-07

Applicant: United Microelectronics Corp.

Inventor： Hui Liu

IPC: G03F7/20 ,  H01L23/544

CPC classification number: G03F7/70633 ,  H01L23/544 ,  H01L2223/54426

Abstract: An overlay target includes a plurality of working zones, a plurality of holes in each of the working zones, and a first layer filling in the plurality of holes. The plurality of holes are not filled up by the first layer, and a plurality of spaces are reserved in the plurality of holes.

公开(公告)号：US11944016B2

公开(公告)日：2024-03-26

申请号：US17692203

申请日：2022-03-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

Abstract: A magnetoresistive random access memory, including a substrate, a conductive plug in the substrate, wherein the conductive plug has a notched portion on one side of the upper edge of the conductive plug, and a magnetic memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction on the bottom electrode and a top electrode on the magnetic tunnel junction, wherein the bottom surface of the magnetic memory cell and the top surface of the conductive plug completely align and overlap each other.

公开(公告)号：US11942130B2

公开(公告)日：2024-03-26

申请号：US17701703

申请日：2022-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Jhong Chen ,  Yi-Ting Wu ,  Jen-Yu Wang ,  Cheng-Tung Huang ,  Po-Chun Yang ,  Yung-Ching Hsieh

IPC: G11C11/00 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85 ,  G11C11/15 ,  G11C11/165

Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

公开(公告)号：US11935947B2

公开(公告)日：2024-03-19

申请号：US16596738

申请日：2019-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Shin-Chuan Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/49

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/7787

Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.

公开(公告)号：US20240090342A1

公开(公告)日：2024-03-14

申请号：US18511984

申请日：2023-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Ya-Sheng Feng

IPC: H10N50/80 ,  H01L21/768 ,  H10N50/01

CPC classification number: H10N50/80 ,  H01L21/76801 ,  H01L21/76838 ,  H10N50/01

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.