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    THREE DIMENSIONAL MEMORY DEVICE AND DATA ERASE METHOD THEREOF
    151.
    发明申请
    THREE DIMENSIONAL MEMORY DEVICE AND DATA ERASE METHOD THEREOF 有权
    三维存储器件及其数据擦除方法

    公开(公告)号：US20160012901A1

    公开(公告)日：2016-01-14

    申请号：US14330106

    申请日：2014-07-14

    Applicant: Macronix International Co., Ltd.

    Inventor： Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Chen-Jun Wu

    IPC: G11C16/16 ,  G11C16/04

    CPC classification number: G11C16/16 ,  G11C16/0408 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

    Abstract: A data erase method of a three dimensional (3D) memory device comprising the following steps. First, in a first phase of an erase operation, a first voltage is applied to a first semiconductor channel of the semiconductor channels to erase data stored in the memory cells defined on the first semiconductor channel and a second voltage is applied to a second semiconductor channel of the semiconductor channels, wherein the second semiconductor channel is adjacent to the first semiconductor channel. Then, in a second phase of the erase operation, the second voltage is applied to the first semiconductor channel and the first voltage is applied to the second semiconductor channel.

    Abstract translation: 一种三维（3D）存储器件的数据擦除方法，包括以下步骤。 首先，在擦除操作的第一阶段中，将第一电压施加到半导体通道的第一半导体通道，以擦除存储在第一半导体通道上限定的存储单元中的数据，并将第二电压施加到第二半导体通道 的半导体通道，其中第二半导体沟道与第一半导体沟道相邻。 然后，在擦除操作的第二阶段中，将第二电压施加到第一半导体沟道，并将第一电压施加到第二半导体沟道。

    Hot carrier generation and programming in NAND flash
    154.
    发明授权
    Hot carrier generation and programming in NAND flash 有权
    NAND闪存中的热载波生成和编程

    公开(公告)号：US09171636B2

    公开(公告)日：2015-10-27

    申请号：US13940010

    申请日：2013-07-11

    Applicant: Macronix International Co., Ltd.

    Inventor： Kuo-Pin Chang ,  Wen-Wei Yeh ,  Chih-Shen Chang ,  Hang-Ting Lue

    IPC: G11C16/00 ,  G11C16/34

    CPC classification number: G11C16/3459 ,  G11C16/3427

    Abstract: A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The control circuitry is adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting.

    Abstract translation: 描述了一种存储器件，其包括具有由多个字线访问的多个级别的存储器单元的存储器单元的三维阵列以及多个位线。 控制电路耦合到多个字线和多个位线。 控制电路适用于通过热载流子生成辅助FN隧道在阵列的选定电平和所选择的字线上对选定的存储单元进行编程，同时抑制未选择的电平和所选电平中的未选定存储单元的干扰 未经选择的字线通过自我提升。

    Three-dimensional memory device
    155.
    发明授权
    Three-dimensional memory device 有权
    三维存储设备

    公开(公告)号：US09087736B1

    公开(公告)日：2015-07-21

    申请号：US14449305

    申请日：2014-08-01

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Hang-Ting Lue

    IPC: H01L23/52 ,  H01L27/115

    CPC classification number: H01L27/11551 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

    Abstract: A 3D memory device comprising a memory unit block, a first stair-step structure, a second stair-step structure, a first conductive strip and a second conductive strip is provided. The memory unit block comprises a first stacked structure comprising a first semiconductor strip and a second stacked structure comprising a second semiconductor strip. The first stair-step structure is disposed on one side of the memory unit block. The second stair-step structure is disposed on an opposite side of the memory unit block. The first conductive strip electrically coupled to the first semiconductor strip via the first stair-step structure. The second conductive strip electrically coupled to the second semiconductor strip via the second stair-step structure.

    Abstract translation: 提供了一种包括存储器单元块，第一阶梯结构，第二阶梯结构，第一导电条和第二导电条的3D存储器件。 存储器单元块包括第一堆叠结构，其包括第一半导体条和包括第二半导体条的第二堆叠结构。 第一台阶结构设置在存储单元块的一侧。 第二台阶结构设置在存储单元块的相对侧。 第一导电条通过第一阶梯结构电耦合到第一半导体条。 所述第二导电带经由所述第二台阶结构电耦合到所述第二半导体条。

    3D memory array with improved SSL and BL contact layout
    156.
    发明授权
    3D memory array with improved SSL and BL contact layout 有权
    3D内存阵列具有改进的SSL和BL联系布局

    公开(公告)号：US09024374B2

    公开(公告)日：2015-05-05

    申请号：US14513721

    申请日：2014-10-14

    Applicant: Macronix International Co., Ltd.

    Inventor： Chun Hsiung Hung ,  Hang-Ting Lue ,  Shin-Jang Shen

    IPC: H01L29/792 ,  H01L27/115 ,  H01L27/24 ,  H01L23/525 ,  H01L29/423 ,  H01L21/768

    CPC classification number: H01L27/11578 ,  G11C13/0002 ,  G11C16/0483 ,  G11C17/16 ,  G11C2213/71 ,  H01L21/768 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips. Some embodiments include SSL interconnects on a metal layer parallel to the semiconductor material strips, and further SSL interconnects on a higher metal layer, parallel to the word lines.

    Abstract translation: 3D存储器件包括多个脊，在一些实施例中，以绝缘材料隔开的多条导电材料形式的脊形形状，排列成可通过解码电路耦合到读出放大器的位线。 导电材料条具有堆叠侧面上的侧表面。 布置成可以耦合到行解码器的字线的多个导线在多个堆叠上正交延伸。 导线符合堆叠的表面。 存储器元件位于叠层和导电线上的半导体材料条的侧表面之间的交叉点处的界面区域的多层阵列。 存储器元件是可编程的，如抗熔丝或电荷捕获结构。 在一些实施例中，仅使用用于多个层的两个临界掩模来制作3D存储器。 一些实施例包括位于半导体材料条的端部处的阶梯状结构。 一些实施例包括平行于半导体材料带的金属层上的SSL互连以及平行于字线的较高金属层上的另外的SSL互连。

    3D MEMORY ARRAY WITH IMPROVED SSL AND BL CONTACT LAYOUT
    157.
    发明申请
    3D MEMORY ARRAY WITH IMPROVED SSL AND BL CONTACT LAYOUT 审中-公开
    具有改进的SSL和BL联系布局的3D存储阵列

    公开(公告)号：US20150054057A1

    公开(公告)日：2015-02-26

    申请号：US14513721

    申请日：2014-10-14

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chun Hsiung Hung ,  Hang-Ting Lue ,  Shin-Jang Shen

    IPC: H01L27/115 ,  H01L21/768 ,  H01L29/423 ,  H01L27/24 ,  H01L23/525

    CPC classification number: H01L27/11578 ,  G11C13/0002 ,  G11C16/0483 ,  G11C17/16 ,  G11C2213/71 ,  H01L21/768 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips. Some embodiments include SSL interconnects on a metal layer parallel to the semiconductor material strips, and further SSL interconnects on a higher metal layer, parallel to the word lines.

    Abstract translation: 3D存储器件包括多个脊，在一些实施例中，以绝缘材料隔开的多条导电材料形式的脊形形状，排列成可通过解码电路耦合到读出放大器的位线。 导电材料条具有堆叠侧面上的侧表面。 布置成可以耦合到行解码器的字线的多个导线在多个堆叠上正交延伸。 导线符合堆叠的表面。 存储器元件位于叠层和导电线上的半导体材料条的侧表面之间的交叉点处的界面区域的多层阵列。 存储器元件是可编程的，如抗熔丝或电荷捕获结构。 在一些实施例中，仅使用用于多层的两个临界掩模来制作3D存储器。 一些实施例包括位于半导体材料条的端部处的阶梯状结构。 一些实施例包括平行于半导体材料带的金属层上的SSL互连以及平行于字线的较高金属层上的另外的SSL互连。

    MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME
    158.
    发明申请
    MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
    存储器件及其制造方法

    公开(公告)号：US20150048506A1

    公开(公告)日：2015-02-19

    申请号：US13965269

    申请日：2013-08-13

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yi-Hsuan Hsiao ,  Yen-Hao Shih ,  Shih-Hung Chen ,  Hang-Ting Lue

    IPC: H01L27/06 ,  H01L27/105 ,  H01L27/12

    CPC classification number: H01L27/0688 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578

    Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a conductive connection structure. The 3D memory array and the periphery circuit are stacked on the substrate. The periphery circuit includes a patterned metal layer and a contact structure electrically connected to the patterned metal layer. The conductive connection structure is electrically connected to the patterned metal layer. The 3D memory array is electrically connected to the periphery circuit via the conductive connection structure.

    Abstract translation: 提供了一种存储器件及其制造方法。 存储器件包括衬底，3D存储器阵列，外围电路和导电连接结构。 3D存储器阵列和外围电路堆叠在基板上。 外围电路包括图案化金属层和电连接到图案化金属层的接触结构。 导电连接结构电连接到图案化的金属层。 3D存储器阵列经由导电连接结构电连接到外围电路。

    Silicon on insulator and thin film transistor bandgap engineered split gate memory
    159.
    发明授权
    Silicon on insulator and thin film transistor bandgap engineered split gate memory 有权
    硅绝缘体和薄膜晶体管带隙设计的分离栅极存储器

    公开(公告)号：US08937340B2

    公开(公告)日：2015-01-20

    申请号：US13899629

    申请日：2013-05-22

    Applicant: Macronix International Co., Ltd.

    Inventor： Hang-Ting Lue ,  Erh-Kun Lai

    IPC: H01L23/52 ,  H01L29/66 ,  G11C16/04 ,  H01L21/28 ,  H01L27/115 ,  H01L29/792

    CPC classification number: H01L29/66833 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792

    Abstract: Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.

    Abstract translation: 存储单元包括薄膜晶体管，堆叠阵列，采用无接合的NAND配置的带隙工程隧道层。 单元包括在绝缘层上形成的半导体条中的沟道区; 隧道电介质结构，其设置在所述沟道区上方，所述隧道介电结构包括多层结构，所述多层结构包括至少一层，所述层具有低于与所述沟道区的界面处的空穴 - 设置在隧道介电结构上方的电荷存储层; 设置在电荷存储层上方的绝缘层; 并且设置在绝缘层上方的栅电极描述了阵列和操作方法。

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