公开(公告)号：US20160365350A1

公开(公告)日：2016-12-15

申请号：US15245539

申请日：2016-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3215 ,  H01L29/423 ,  H01L21/3213

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/32139 ,  H01L21/32155 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11541 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: A method of manufacturing an embedded flash memory device is provided. A pair of gate stacks are formed spaced over a semiconductor substrate, and including floating gates and control gates over the floating gates. A common gate layer is formed over the gate stacks and the semiconductor substrate, and lining sidewalls of the gate stacks. A first etch is performed into the common gate layer to recess an upper surface of the common gate layer to below upper surfaces respectively of the gate stacks, and to form an erase gate between the gate stacks. Hard masks are respectively formed over the erase gate, a word line region of the common gate layer, and a logic gate region of the common gate layer. A second etch is performed into the common gate layer with the hard masks in place to concurrently form a word line and a logic gate.

Abstract translation: 提供了一种制造嵌入式闪存设备的方法。 一对栅极叠层形成在半导体衬底上间隔开，并且在浮动栅极上包括浮动栅极和控制栅极。 在栅极堆叠和半导体衬底上形成公共栅极层，并且栅极堆叠的衬里侧壁。 在公共栅极层中执行第一蚀刻，以将公共栅极层的上表面分别凹入栅极堆叠的下表面，并在栅极堆叠之间形成擦除栅极。 硬掩模分别形成在擦除栅极，公共栅极层的字线区域和公共栅极层的逻辑门极区域上。 第二蚀刻被执行到具有硬掩模的公共栅层中，以同时形成字线和逻辑门。

公开(公告)号：US09484352B2

公开(公告)日：2016-11-01

申请号：US14573208

申请日：2014-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/788 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/32139 ,  H01L21/32155 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11541 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: An embedded flash memory device is provided. A gate stack includes a control gate arranged over a floating gate. An erase gate is arranged adjacent to a first side of the gate stack. A word line is arranged adjacent to a second side of the gate stack that is opposite the first side. The word line includes a word line ledge exhibiting a reduced height relative to a top surface of the word line and on an opposite side of the word line as the gate stack. A polysilicon logic gate has a top surface approximately even with the word line ledge. An ILD layer is arranged over the gate stack, the erase gate, the polysilicon logic gate, and the word lines. A contact extends through the ILD layer. A method of manufacturing the embedded flash memory device is also provided.

Abstract translation: 提供了一种嵌入式闪存设备。 栅极堆叠包括布置在浮动栅极上的控制栅极。 擦除栅极邻近栅堆叠的第一侧布置。 字线布置成与栅堆叠的与第一侧相对的第二侧相邻。 字线包括字线凸出部，该字线突出部相对于字线的顶表面减小高度，并且与字线堆叠在字线的相反侧。 多晶硅逻辑门具有大致均匀的字线凸缘的顶表面。 ILD层布置在栅极堆叠，擦除栅极，多晶硅逻辑门和字线之上。 一个触点延伸穿过ILD层。 还提供了一种制造嵌入式闪存设备的方法。

公开(公告)号：US20160225846A1

公开(公告)日：2016-08-04

申请号：US14851357

申请日：2015-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Yu-Hsiung Wang ,  Chen-Chin Liu

IPC: H01L49/02 ,  H01L27/115

CPC classification number: H01L28/90 ,  H01L27/0629 ,  H01L27/10805 ,  H01L27/1157 ,  H01L27/11573 ,  H01L28/40 ,  H01L29/517 ,  H01L29/66545

Abstract: Some embodiments of the present disclosure relate to an integrated circuit (IC) arranged on a semiconductor substrate, which includes a flash region, a capacitor region, and a logic region. An upper substrate surface of the capacitor region is recessed relative to respective upper substrate surfaces of the flash and logic regions, respectively. A capacitor, which includes a polysilicon bottom electrode, a conductive top electrode arranged over the polysilicon bottom electrode, and a capacitor dielectric separating the bottom and top electrodes; is disposed over the recessed upper substrate surface of the capacitor region. A flash memory cell is disposed over the upper substrate surface of the flash region. The flash memory cell includes a select gate having a planarized upper surface that is co-planar with a planarized upper surface of the top electrode of the capacitor.

Abstract translation: 本公开的一些实施例涉及布置在半导体衬底上的集成电路（IC），其包括闪存区域，电容器区域和逻辑区域。 电容器区域的上基板表面分别相对于闪光和逻辑区域的相应上基板表面凹陷。 一种电容器，其包括多晶硅底部电极，布置在所述多晶硅底部电极上的导电顶部电极以及分离所述底部和顶部电极的电容器电介质; 设置在电容器区域的凹陷的上基板表面上。 闪存单元设置在闪光区域的上基板表面上。 闪存单元包括具有与电容器的顶部电极的平坦化上表面共面的平坦化上表面的选择栅极。

公开(公告)号：US20160181268A1

公开(公告)日：2016-06-23

申请号：US14580454

申请日：2014-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Fang-Lan Chu

IPC: H01L27/115

CPC classification number: H01L27/11573 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11575 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.

Abstract translation: 本公开涉及用于减少集成电路中的CMP凹陷的结构和方法。 在一些实施例中，该结构具有具有嵌入的存储区域和外围区域的半导体衬底。 在存储区域和外围区域之间形成一个或多个虚拟结构。 在嵌入的存储区域和外围区域之间的虚拟结构的放置使得其之间的沉积层的表面在抛光之后变得更平坦，而不会产生凹陷效应。 减少的凹陷减少金属残留物的形成，从而导致金属残留物导致的电流泄漏和短路。 此外，较少的凹陷将减少有源器件的多晶硅损耗。 在一些实施例中，虚拟结构之一形成有成角度的侧壁，其消除了对边界切割蚀刻工艺的需要。

公开(公告)号：US20160181266A1

公开(公告)日：2016-06-23

申请号：US14573208

申请日：2014-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/32139 ,  H01L21/32155 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11541 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: An embedded flash memory device is provided. A gate stack includes a control gate arranged over a floating gate. An erase gate is arranged adjacent to a first side of the gate stack. A word line is arranged adjacent to a second side of the gate stack that is opposite the first side. The word line includes a word line ledge exhibiting a reduced height relative to a top surface of the word line and on an opposite side of the word line as the gate stack. A polysilicon logic gate has a top surface approximately even with the word line ledge. An ILD layer is arranged over the gate stack, the erase gate, the polysilicon logic gate, and the word lines. A contact extends through the ILD layer. A method of manufacturing the embedded flash memory device is also provided.

Abstract translation: 提供了一种嵌入式闪存设备。 栅极堆叠包括布置在浮动栅极上的控制栅极。 擦除栅极邻近栅堆叠的第一侧布置。 字线布置成与栅堆叠的与第一侧相对的第二侧相邻。 字线包括字线凸出部，该字线突出部相对于字线的顶表面减小高度，并且与字线堆叠在字线的相反侧。 多晶硅逻辑门具有大致均匀的字线凸缘的顶表面。 ILD层布置在栅极堆叠，擦除栅极，多晶硅逻辑门和字线之上。 一个触点延伸穿过ILD层。 还提供了一种制造嵌入式闪存设备的方法。

公开(公告)号：US20160181261A1

公开(公告)日：2016-06-23

申请号：US14580505

申请日：2014-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Harry-Hak-Lay Chuang ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/76229 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548

Abstract: The present disclosure relates a method of forming an integrated circuit. In some embodiments, the method is performed by patterning a first masking layer over a substrate to have a first plurality of openings at a memory cell region and a second plurality of openings at a boundary region. A first plurality of dielectric bodies are formed within the first plurality of openings and a second plurality of dielectric bodies are formed within the second plurality of openings. A second masking layer is formed over the first masking layer and the first and second plurality of dielectric bodies. The first and second masking layers are removed at the memory cell region, and a first conductive layer is formed to fill recesses between the first plurality of dielectric bodies. A planarization process reduces a height of the first conductive layer and removes the first conductive layer from over the boundary region.

Abstract translation: 本公开涉及一种形成集成电路的方法。 在一些实施例中，该方法通过在衬底上图案化第一掩模层来进行，以在存储单元区域处具有第一多个开口，并在边界区域具有第二多个开口。 在所述第一多个开口内形成有第一多个介电体，并且在所述第二多个开口内形成第二多个介电体。 在第一掩蔽层和第一和第二多个电介质体之上形成第二掩模层。 在存储单元区域处去除第一和第二掩模层，并且形成第一导电层以填充第一多个电介质体之间的凹部。 平坦化处理降低了第一导电层的高度，并从边界区域上移除第一导电层。

公开(公告)号：US20160133636A1

公开(公告)日：2016-05-12

申请号：US14980147

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu

IPC: H01L27/115 ,  H01L21/321 ,  H01L21/306 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/3212 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1116 ,  H01L27/11546 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/66545

Abstract: An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

Abstract translation: 嵌入式闪速存储器件包括栅堆叠，其包括延伸到半导体衬底中的凹部中的底部电介质层和位于底部电介质层上的电荷存储层。 电荷存储层包括凹部中的一部分。 栅极堆叠还包括电荷存储层上的顶部电介质层，以及在顶部电介质层上方的金属栅极。 源极和漏极区位于半导体衬底中，并且位于栅堆叠的相对侧上。

公开(公告)号：US09287279B2

公开(公告)日：2016-03-15

申请号：US14225874

申请日：2014-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Wei Cheng Wu ,  Harry-Hak-Lay Chuang

IPC: H01L27/115 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation.

Abstract translation: 一些实施例涉及具有纳米晶体的电荷捕获层的存储器单元，其包括沿着选择栅极的隧穿氧化物层，形成在控制栅极和隧道氧化物层之间的控制氧化物层，以及多个纳米晶体，其布置在隧道 并控制氧化物层。 封装层将纳米晶体与控制氧化物层隔离。 与选择栅极的接触形成包括两步蚀刻。 第一蚀刻包括氧化物和封装层之间的选择性，并且蚀刻掉控制氧化物层，同时保持封装层完好无损。 具有与第一蚀刻相反的选择性的第二蚀刻然后在完全留下隧道氧化物层的同时蚀刻封装层。 结果，将控制氧化物层和纳米晶体从选择栅极的表面蚀刻掉，同时使隧道氧化物层完好无损以进行接触隔离。

公开(公告)号：US20160020219A1

公开(公告)日：2016-01-21

申请号：US14332556

申请日：2014-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Kai-Shyang You

IPC: H01L27/115 ,  H01L29/423 ,  H01L21/265 ,  H01L29/06 ,  H01L29/49 ,  H01L21/28 ,  H01L27/12 ,  H01L29/51

CPC classification number: H01L21/265 ,  H01L21/26513 ,  H01L21/28017 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/42344 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/792

Abstract: Some embodiments of the present disclosure provide an integrated circuit arranged on a silicon-on-insulator (SOI) substrate region. The SOI substrate region is made up of a handle wafer region, an oxide layer arranged over the handle wafer region, and a silicon layer arranged over the oxide layer. A recess extends downward from an upper surface of the silicon layer and terminates in the handle wafer region, thereby defining a recessed handle wafer surface and sidewalls extending upwardly from the recessed handle wafer surface to meet the upper surface of the silicon layer. A first semiconductor device is disposed on the recessed handle wafer surface. A second semiconductor device is disposed on the upper surface of the silicon layer.

Abstract translation: 本公开的一些实施例提供了布置在绝缘体上硅（SOI）衬底区域上的集成电路。 SOI衬底区域由处理晶片区域，布置在处理晶片区域上的氧化物层和布置在氧化物层上的硅层构成。 凹部从硅层的上表面向下延伸并且终止于处理晶片区域，从而限定凹入的处理晶片表面和从凹入的处理晶片表面向上延伸以与硅层的上表面相遇的侧壁。 第一半导体器件设置在凹入的处理晶片表面上。 第二半导体器件设置在硅层的上表面上。

公开(公告)号：US20160005756A1

公开(公告)日：2016-01-07

申请号：US14324369

申请日：2014-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/11573 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

Abstract translation: 本公开涉及一种用于在包括高电压（HV）HKMG晶体管的HKMG（高金属栅极）集成电路中嵌入非易失性存储器（NVM）的结构和方法。 NVM设备（例如，闪速存储器）在高电压下操作用于其读取和写入操作，因此HV器件对于涉及非易失性嵌入式存储器和HKMG逻辑电路的集成电路是必需的。 与HKMG外围电路一起形成HV HKMG电路减少了HV晶体管与外围电路的其余部分之间的附加边界的需要。 该方法进一步有助于减少divot问题并减少单元大小。