公开(公告)号：US20230409341A1

公开(公告)日：2023-12-21

申请号：US18312237

申请日：2023-05-04

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics International N.V.

Inventor： Asif Rashid Zargar ,  Roberto Colombo

IPC: G06F9/4401 ,  G06F21/64

CPC classification number: G06F9/4405 ,  G06F21/64

Abstract: In embodiments, a reset management circuit executes reset, configuration, and software runtime phases when a processing system is switched on, where one or more microprocessors start at respective start addresses. During the configuration phase, a circuit reads a boot record from a non-volatile memory and stores it to registers. The circuit sequentially reads data records of configuration data from the non-volatile memory and generates a write request for each data record to store the data of the respective data record to a second circuit with associated address data indicated in the respective data record. The processing system processes the boot record and boot configuration data provided by the second circuits to selectively start a predetermined microprocessor at a default start address or at a start address indicated by the boot configuration data, or start one or more microprocessors at respective start addresses as indicated by the boot record.

公开(公告)号：US20230396155A1

公开(公告)日：2023-12-07

申请号：US17834174

申请日：2022-06-07

Applicant: STMicroelectronics International N.V.

Inventor： Ranajay MALLIK ,  Akshat JAIN

IPC: H02M1/42 ,  H02M1/12

CPC classification number: H02M1/4216 ,  H02M1/4225 ,  H02M1/4233 ,  H02M1/12

Abstract: A PFC correction circuit includes first, second, and third phase inputs coupled to three-phase power mains, with a three-phase full-wave rectifying bridge connected to an input node. First, second, and third boost inductors are respectively connected between first, second, and third phase inputs and first, second, and third taps of the three-phase full-wave rectifying bridge. A boost switch is connected between the input node and ground, and a boost diode is connected between the input node and an output node. A multiplier input driver generates a single-phase input signal as a replica of a signal at the three-phase power mains after rectification. A single-phase power factor controller generates a PWM signal from the single-phase input signal. A gate driver generates a gate drive signal from the PWM signal. The boost switch is operated by the gate drive signal.

公开(公告)号：US11835991B2

公开(公告)日：2023-12-05

申请号：US17208935

申请日：2021-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Amulya Pandey ,  Balwinder Singh Soni ,  Amritanshu Anand ,  Venkata Narayanan Srinivasan

IPC: G06F11/27 ,  G01R31/3177 ,  G06F1/08

CPC classification number: G06F11/27 ,  G01R31/3177 ,  G06F1/08

Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.

公开(公告)号：US11829730B2

公开(公告)日：2023-11-28

申请号：US17940654

申请日：2022-09-08

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin Chawla ,  Tanmoy Roy ,  Anuj Grover ,  Giuseppe Desoli

IPC: G06F7/57 ,  G06F3/06 ,  G06N3/063

CPC classification number: G06F7/57 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06N3/063

Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

公开(公告)号：US11798603B2

公开(公告)日：2023-10-24

申请号：US18175375

申请日：2023-02-27

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Vivek Tyagi ,  Vikas Rana ,  Chantal Auricchio ,  Laura Capecchi

IPC: G11C7/12 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4091 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C7/222 ,  G11C11/4091 ,  G11C11/4094

Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.

公开(公告)号：US20230314506A1

公开(公告)日：2023-10-05

申请号：US18186624

申请日：2023-03-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH

Inventor： Roberto Colombo ,  Vivek Mohan Sharma

IPC: G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/31721 ,  G01R31/31724 ,  G01R31/318566

Abstract: In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.

公开(公告)号：US11758707B2

公开(公告)日：2023-09-12

申请号：US17118372

申请日：2020-12-10

Applicant: STMicroelectronics International N.V.

Inventor： Shafquat Jahan Ahmed ,  Kedar Janardan Dhori

IPC: H10B10/00

CPC classification number: H10B10/12 ,  H10B10/18

Abstract: A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.

公开(公告)号：US11749343B2

公开(公告)日：2023-09-05

申请号：US17578086

申请日：2022-01-18

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin Chawla ,  Tanmoy Roy ,  Anuj Grover

IPC: G11C13/00 ,  G06F9/50 ,  G11C29/00 ,  G11C29/26 ,  G11C29/44 ,  G06N3/063

CPC classification number: G11C13/004 ,  G06F9/5016 ,  G06N3/063 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  G11C29/006 ,  G11C29/26 ,  G11C2029/4402 ,  G11C2211/561

Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.

公开(公告)号：US11742799B2

公开(公告)日：2023-08-29

申请号：US17750137

申请日：2022-05-20

Applicant: STMicroelectronics International N.V.

Inventor： Kapil Kumar Tyagi

IPC: H03B5/12 ,  H03L5/00 ,  H03K3/03

CPC classification number: H03B5/1265 ,  H03L5/00 ,  H03B2200/003 ,  H03K3/0315

Abstract: A voltage controlled oscillator (VCO) has a VCO core and a tuning bank. The tuning bank includes first and second tuning capacitors. A main switch is coupled between the first and second tuning capacitors. The tuning bank also includes control switches that receive a control signal to selectively activate the tuning bank. The main switch receives a level-shifted control signal to activate the tuning bank.

公开(公告)号：US20230251829A1

公开(公告)日：2023-08-10

申请号：US18134737

申请日：2023-04-14

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Rupesh SINGH

IPC: G06F7/548 ,  H03K3/037 ,  G06F7/544 ,  H03K5/01

CPC classification number: G06F7/548 ,  H03K3/037 ,  G06F7/5443 ,  H03K5/01 ,  H03K2005/00078

Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.