公开(公告)号：US20050253794A1

公开(公告)日：2005-11-17

申请号：US10907159

申请日：2005-03-23

Applicant: Ssu-Ming Lee ,  Seob Shin ,  Feng-Ting Pai ,  Hsien-Wen Chou

Inventor： Ssu-Ming Lee ,  Seob Shin ,  Feng-Ting Pai ,  Hsien-Wen Chou

IPC: G09G3/36

CPC classification number: G09G3/3648 ,  G09G3/3677 ,  G09G2310/061

Abstract: An impulse driving method and apparatus thereof for a liquid crystal display (LCD) are provided. The gate driver of the liquid crystal device generates first scan signals for controlling gate lines of the liquid crystal device according to the received first start vertical signal and first output enable signal. The scan signals are generated corresponding to the pixel data signals outputted from the data driver of the LCD. Moreover, the gate driver of the LCD generates second scan signals according to the received second start vertical signal and second output enable signals. The scan signals are generated corresponding to black data signals output from the data driver of the liquid crystal device. Therefore, the control signal scheme is simplified and the black insertion ratio is easily controlled.

Abstract translation: 提供了一种用于液晶显示器（LCD）的脉冲驱动方法及其装置。 液晶装置的栅极驱动器根据接收到的第一起始垂直信号和第一输出使能信号产生用于控制液晶装置的栅极线的第一扫描信号。 对应于从LCD的数据驱动器输出的像素数据信号产生扫描信号。 此外，LCD的栅极驱动器根据接收的第二起始垂直信号和第二输出使能信号产生第二扫描信号。 对应于从液晶装置的数据驱动器输出的黑色数据信号产生扫描信号。 因此，简化了控制信号方案，并且容易地控制黑色插入率。

公开(公告)号：US20050200297A1

公开(公告)日：2005-09-15

申请号：US11063283

申请日：2005-02-22

Applicant: Kun-Ming Lee ,  Tsung-Wei Huang

Inventor： Kun-Ming Lee ,  Tsung-Wei Huang

IPC: H05B37/00

CPC classification number: B41J2/0458 ,  B41J2/04541 ,  B41J2/04543

Abstract: A fluid jet head with driving circuit of a heater set. A first and a second primary transistor are coupled to a first and a second heater. When the first primary transistor is turned on under control of a first control voltage and a first current is generated flowing through the first heater, the first primary transistor, and the first current path, then the first primary transistor has a first primary equivalent resistance corresponding to the first control voltage. When the second primary transistor is turned on under control of a second control voltage, and a second current is generated flowing through the second heater, the second primary transistor, and a second current path, then the second primary transistor has a second primary equivalent resistance corresponding to the second control voltage. Therefore, the thermal energy generated by the first heater is substantially equal to that generated by the second heater.

Abstract translation: 具有加热器组的驱动电路的流体喷射头。 第一和第二初级晶体管耦合到第一和第二加热器。 当在第一控制电压的控制下第一初级晶体管导通并且产生流过第一加热器，第一初级晶体管和第一电流路径的第一电流时，第一初级晶体管具有对应的第一初级等效电阻 到第一控制电压。 当第二主晶体管在第二控制电压的控制下导通时，产生流经第二加热器，第二主晶体管和第二电流路径的第二电流，则第二初级晶体管具有第二初级等效电阻 对应于第二控制电压。 因此，由第一加热器产生的热能基本上等于由第二加热器产生的热能。

公开(公告)号：US20050189075A1

公开(公告)日：2005-09-01

申请号：US10789660

申请日：2004-02-27

Applicant: Shing-Chyang Pan ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Li-Lin Su ,  Shau-Lin Shue

Inventor： Shing-Chyang Pan ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Li-Lin Su ,  Shau-Lin Shue

IPC: B08B7/00 ,  H01J37/32 ,  H01L21/00 ,  C23F1/00

CPC classification number: H01L21/67109 ,  B08B7/0071 ,  H01J37/32862

Abstract: A reactive pre-clean chamber that contains a wafer heating apparatus, such as a high-temperature electrostatic chuck (HTESC), for directly heating a wafer supported on the apparatus during a pre-cleaning process. The wafer heating apparatus is capable of heating the wafer to the optimum temperatures required for a hydrogen plasma reactive pre-clean (RPC) process. Furthermore, degassing and pre-cleaning can be carried out in the same pre-clean chamber. The invention further includes a method of pre-cleaning a wafer using a pre-clean chamber that contains a wafer heating apparatus.

Abstract translation: 一种反应性预清洁室，其包含诸如高温静电卡盘（HTESC）的晶片加热装置，用于在预清洁过程期间直接加热支撑在装置上的晶片。 晶片加热装置能够将晶片加热到氢等离子体反应性预清洁（RPC）工艺所需的最佳温度。 此外，脱气和预清洁可以在相同的预清洁室中进行。 本发明还包括使用包含晶片加热装置的预清洁室预清洁晶片的方法。

公开(公告)号：US20050184344A1

公开(公告)日：2005-08-25

申请号：US10787678

申请日：2004-02-25

Applicant: Ming-Dou Ker ,  Cheng-Ming Lee ,  Tung-Yang Chen

Inventor： Ming-Dou Ker ,  Cheng-Ming Lee ,  Tung-Yang Chen

IPC: H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H02H9/00

CPC classification number: H01L27/0288 ,  H01L23/60 ,  H01L24/06 ,  H01L27/0255 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An ESD protection circuit design incorporating a single, or a plurality of, parallel inductor and capacitor, also known as LC tank(s), to avoid power loss by parasitic capacitance in ESD circuits. The first design described incorporates a LC tank structure. The second includes two LC tank structures. These structures can be expanded to form ESD protection circuit structures stacked with n-stages LC tanks. The last design described is ESD protection circuits formed by stacking the first design. These designs can avoid power gain loss from parasitic capacitance of ESD, because the parameters of LC tank can be designed to resonant at a desired operating frequency. Each of these designs can be altered slightly to create variant designs with equal identical ESD protection capabilities.

Abstract translation: 包括单个或多个并联电感器和电容器（也称为LC箱）的ESD保护电路设计，以避免ESD电路中的寄生电容的功率损耗。 所描述的第一个设计包括一个LC液箱结构。 第二个包括两个LC坦克结构。 这些结构可以扩展，形成堆积在n级液晶盒中的ESD保护电路结构。 所描述的最后一个设计是通过堆叠第一设计形成的ESD保护电路。 这些设计可以避免由ESD寄生电容引起的功率增益损失，因为LC槽的参数可以设计成在所需工作频率下谐振。 这些设计中的每一个都可以稍微修改，以创建具有相同ESD保护功能的变体设计。

公开(公告)号：US20050179095A1

公开(公告)日：2005-08-18

申请号：US10908114

申请日：2005-04-28

Applicant: Ching-Hsiang Hsu ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Hai-Ming Lee

Inventor： Ching-Hsiang Hsu ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Hai-Ming Lee

IPC: G11C16/04 ,  G11C16/10 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76 ,  H01L29/792

CPC classification number: H01L27/11568 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/115 ,  H01L29/7923

Abstract: A memory cell is disclosed. The memory cell includes an N-well, three P-type doped regions formed on the N-type well, a first stacked dielectric layer formed on the N-type well and between a first doped region and a second doped region from among the three P-type doped regions, a first gate formed on the first stacked dielectric layer, a second stacked dielectric layer formed on the N-type well and between the second doped region and a third doped region from among the three P-type doped regions, and a second gate formed on the second stacked dielectric layer.

Abstract translation: 公开了一种存储器单元。 存储单元包括N阱，形成在N型阱上的三个P型掺杂区，形成在N型阱上的第一层叠电介质层，以及在三层阱中的第一掺杂区和第二掺杂区之间 P型掺杂区域，形成在第一堆叠介质层上的第一栅极，形成在N型阱上的第二堆叠电介质层，以及在三个P型掺杂区域中的第二掺杂区域和第三掺杂区域之间， 以及形成在所述第二堆叠电介质层上的第二栅极。

公开(公告)号：US20050156316A1

公开(公告)日：2005-07-21

申请号：US11070569

申请日：2005-03-02

Applicant: Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chung-Shi Liu ,  Chen-Hua Yu

Inventor： Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L21/285 ,  H01L21/768 ,  H01L23/48 ,  H01L21/31 ,  H01L21/469 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76846 ,  H01L21/2855

Abstract: Within a microelectronic fabrication and a method for fabricating the microelectronic fabrication a barrier layer is formed over a substrate. Within the method and the microelectronic fabrication the barrier layer is formed of a refractory metal nitride barrier material having within its thickness a gradient in nitrogen concentration. The barrier layer has low resistivity and improved electromigration performance.

Abstract translation: 在微电子制造和微电子制造的制造方法中，在衬底上形成阻挡层。 在该方法和微电子制造中，阻挡层由其厚度为氮浓度梯度的难熔金属氮化物阻挡材料形成。 阻挡层具有低电阻率和改善的电迁移性能。

公开(公告)号：US20050145927A1

公开(公告)日：2005-07-07

申请号：US10905056

申请日：2004-12-13

Applicant: Ching-Hsiang Hsu ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Hai-Ming Lee

Inventor： Ching-Hsiang Hsu ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Hai-Ming Lee

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/76

CPC classification number: G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/7923

Abstract: A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well and between the first doped region and the second doped region from among the three P-type doped regions. The first gate is formed on the first stacked dielectric layer. The second stacked dielectric layer is formed on the N-type well and between the second doped region and the third doped region from among the three P-type doped regions. The second gate is formed on the second stacked dielectric layer.

公开(公告)号：US06911875B2

公开(公告)日：2005-06-28

申请号：US10278506

申请日：2002-10-23

Applicant: Chao-Cheng Lee ,  An-Ming Lee

Inventor： Chao-Cheng Lee ,  An-Ming Lee

IPC: H03H7/40 ,  H03H7/38 ,  G06G7/12

CPC classification number: H03H7/40

Abstract: The present invention discloses an impedance matching circuit with automatic adjustment and a method thereof. The impedance matching circuit comprises: a resistor, for receiving a reference voltage and generating a reference current; a detection unit, for detecting resistance variation and generating a plurality of comparison voltages according to said reference current; a comparison unit, for comparing said reference voltage with said comparison voltages, and generating a control signal; and a composite resistor unit, for receiving said control signal and generating a matched impedance. Therefore, a matched impedance value can be obtained within a designed range in despite of the manufacturing process and the operation environment.

Abstract translation: 本发明公开了一种具有自动调整的阻抗匹配电路及其方法。 阻抗匹配电路包括：电阻器，用于接收参考电压并产生参考电流; 检测单元，用于检测电阻变化并根据所述参考电流产生多个比较电压; 比较单元，用于将所述参考电压与所述比较电压进行比较，并产生控制信号; 以及用于接收所述控制信号并产生匹配阻抗的复合电阻器单元。 因此，尽管制造过程和操作环境都能在设计范围内获得匹配的阻抗值。

公开(公告)号：US20050100177A1

公开(公告)日：2005-05-12

申请号：US10904343

申请日：2004-11-04

Applicant: ING-MING LEE

Inventor： ING-MING LEE

IPC: H03F1/30 ,  H03G3/34 ,  H04B15/00 ,  H03F1/14

CPC classification number: H03F1/305 ,  H03G3/348

Abstract: The present invention discloses a mute circuit of an audio device for suppressing audio signals during the transients of power switching. A mute circuit for an amplifier having at least an audio output terminal includes at least one bypass device, each of which has a controlling terminal and is capable of providing a path from the audio output terminal to a ground when the controlling terminal is turned on; a power-on controlling circuit for turning on the controlling terminal of the bypass device during a first period of time after a power-on transient; a fixed-voltage supply for stopping the amplifier during the power-on transient according to a control of a controlling terminal of an input/output port; and a power-off controlling circuit for turning on the controlling terminal of the bypass device by utilizing a voltage of a capacitor during a second period of time after a power-off transient.

Abstract translation: 本发明公开了一种音频设备的静音电路，用于在功率切换的瞬变期间抑制音频信号。 用于具有至少音频输出端子的放大器的静音电路包括至少一个旁路装置，每个旁路装置具有控制端子，并且当控制端子接通时能够提供从音频输出端子到地面的路径; 一个上电控制电路，用于在上电瞬态之后的第一时间段内接通旁路装置的控制端; 用于根据输入/输出端口的控制端子的控制在上电瞬变期间停止放大器的固定电压电源; 以及断电控制电路，用于在断电瞬间之后的第二时间段内利用电容器的电压来接通旁路装置的控制端子。

公开(公告)号：US06852567B1

公开(公告)日：2005-02-08

申请号：US09980222

申请日：1999-05-31

Applicant: Charles-Wee-Ming Lee ,  Helmut Strack

Inventor： Charles-Wee-Ming Lee ,  Helmut Strack

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/50 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/3142 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A method of assembling a semiconductor device package includes first attaching a semiconductor device to a die-pad area of a leadframe. Electrical connections are then between electrical contact areas on the semiconductor device and electrical connection areas on the leadframe to form a device/leadframe assembly. An adhesion enhancing coating is then deposited on the exposed surface of the device frame/leadframe assembly before encapsulating the coated device leadframe assembly in an electrically insulating material.

Abstract translation: 一种组装半导体器件封装的方法包括首先将半导体器件附接到引线框的管芯焊盘区域。 然后，电连接在半导体器件上的电接触区域和引线框架上的电连接区域之间，以形成器件/引线框架组件。 然后在将涂覆的装置引线框架组件封装在电绝缘材料中之前，将附着增强涂层沉积在装置框架/引线框组件的暴露表面上。