公开(公告)号：US06852567B1

公开(公告)日：2005-02-08

申请号：US09980222

申请日：1999-05-31

申请人： Charles-Wee-Ming Lee ,  Helmut Strack

发明人： Charles-Wee-Ming Lee ,  Helmut Strack

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/50 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/3142 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A method of assembling a semiconductor device package includes first attaching a semiconductor device to a die-pad area of a leadframe. Electrical connections are then between electrical contact areas on the semiconductor device and electrical connection areas on the leadframe to form a device/leadframe assembly. An adhesion enhancing coating is then deposited on the exposed surface of the device frame/leadframe assembly before encapsulating the coated device leadframe assembly in an electrically insulating material.

摘要翻译： 一种组装半导体器件封装的方法包括首先将半导体器件附接到引线框的管芯焊盘区域。 然后，电连接在半导体器件上的电接触区域和引线框架上的电连接区域之间，以形成器件/引线框架组件。 然后在将涂覆的装置引线框架组件封装在电绝缘材料中之前，将附着增强涂层沉积在装置框架/引线框组件的暴露表面上。

公开(公告)号：US08786012B2

公开(公告)日：2014-07-22

申请号：US13542737

申请日：2012-07-06

申请人： Anton Mauder ,  Franz Hirler ,  Wolfgang Lehnert ,  Rudolf Berger ,  Klemens Pruegl ,  Hans-Joachim Schulze ,  Helmut Strack

发明人： Anton Mauder ,  Franz Hirler ,  Wolfgang Lehnert ,  Rudolf Berger ,  Klemens Pruegl ,  Hans-Joachim Schulze ,  Helmut Strack

IPC分类号： H01L29/66

CPC分类号： H01L21/28194 ,  H01L21/02109 ,  H01L21/02145 ,  H01L21/0228 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66734 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7835 ,  H01L29/792 ,  H01L29/8611

摘要： A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.

摘要翻译： 功率半导体器件具有半导体本体，该半导体本体包括有源区域和限定半导体本体的水平主表面的周边区域。 半导体本体还包括n型半导体层，pn结和至少一个沟槽。 n型半导体层嵌入半导体本体中并延伸到周边区域的主表面。 pn结布置在有源区域中的n型半导体层和主表面之间。 至少一个沟槽在外围区域中从主表面延伸到n型半导体层中，并且包括具有固定的负电荷的电介质层。 在垂直方向上，介电层布置在pn结的下方和上方。 具有固定负电荷的电介质层通常具有负的净电荷。 此外，提供了一种用于形成半导体器件的方法。

公开(公告)号：US08748974B2

公开(公告)日：2014-06-10

申请号：US13542737

申请日：2012-07-06

申请人： Anton Mauder ,  Franz Hirler ,  Wolfgang Lehnert ,  Rudolf Berger ,  Klemens Pruegl ,  Hans-Joachim Schulze ,  Helmut Strack

发明人： Anton Mauder ,  Franz Hirler ,  Wolfgang Lehnert ,  Rudolf Berger ,  Klemens Pruegl ,  Hans-Joachim Schulze ,  Helmut Strack

IPC分类号： H01L29/66

摘要： A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.

公开(公告)号：US08513730B2

公开(公告)日：2013-08-20

申请号：US12021736

申请日：2008-01-29

申请人： Anton Mauder ,  Helmut Strack ,  Armin Willmeroth ,  Hans-Joachim Schulze

发明人： Anton Mauder ,  Helmut Strack ,  Armin Willmeroth ,  Hans-Joachim Schulze

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L21/76224 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/161 ,  H01L29/165 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/7831

摘要： A semiconductor component with vertical structures having a high aspect ratio and method. In one embodiment, a drift zone is arranged between a first and a second component zone. A drift control zone is arranged adjacent to the drift zone in a first direction. A dielectric layer is arranged between the drift zone and the drift control zone wherein the drift zone has a varying doping and/or a varying material composition at least in sections proceeding from the dielectric.

摘要翻译： 具有高纵横比和垂直结构的半导体元件。 在一个实施例中，漂移区布置在第一和第二组分区之间。 漂移控制区在第一方向上布置成与漂移区相邻。 电介质层布置在漂移区和漂移控制区之间，其中漂移区具有至少在从电介质进行的部分中的变化的掺杂和/或变化的材料组成。

公开(公告)号：US20120286355A1

公开(公告)日：2012-11-15

申请号：US13542737

申请日：2012-07-06

申请人： Anton Mauder ,  Franz Hirler ,  Wolfgang Lehnert ,  Rudolf Berger ,  Klemens Pruegl ,  Hans-Joachim Schulze ,  Helmut Strack

发明人： Anton Mauder ,  Franz Hirler ,  Wolfgang Lehnert ,  Rudolf Berger ,  Klemens Pruegl ,  Hans-Joachim Schulze ,  Helmut Strack

IPC分类号： H01L29/78 ,  H01L21/302 ,  H01L29/02

CPC分类号： H01L21/28194 ,  H01L21/02109 ,  H01L21/02145 ,  H01L21/0228 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66734 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7835 ,  H01L29/792 ,  H01L29/8611

摘要： A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.

摘要翻译： 功率半导体器件具有半导体本体，该半导体本体包括有源区域和限定半导体本体的水平主表面的周边区域。 半导体本体还包括n型半导体层，pn结和至少一个沟槽。 n型半导体层嵌入半导体本体中并延伸到周边区域的主表面。 pn结布置在有源区域中的n型半导体层和主表面之间。 至少一个沟槽在外围区域中从主表面延伸到n型半导体层中，并且包括具有固定的负电荷的电介质层。 在垂直方向上，介电层布置在pn结的下方和上方。 具有固定负电荷的电介质层通常具有负的净电荷。 此外，提供了一种用于形成半导体器件的方法。

公开(公告)号：US07947532B2

公开(公告)日：2011-05-24

申请号：US12850902

申请日：2010-08-05

申请人： Ralf Otremba ,  Helmut Strack

发明人： Ralf Otremba ,  Helmut Strack

IPC分类号： H01L21/50 ,  H01L21/44

CPC分类号： H01L23/5389 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/24 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/071 ,  H01L2224/06181 ,  H01L2224/24226 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/8382 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A power semiconductor device and a method for its production. The power semiconductor device has at least one power semiconductor chip, which has on its top side and on its back side large-area electrodes. The electrodes are electrically in connection with external contacts by means of connecting elements, the power semiconductor chip and the connecting elements being embedded in a plastic package. This plastic package has a number of layers of plastic, which are pressed one on top of the other and have plane-parallel upper sides. The connecting elements are arranged on at least one of the plane-parallel upper sides, between the layers of plastic pressed one on top of the other, as a patterned metal layer and are electrically in connection with the external contacts by means of contact vias through at least one of the layers of plastic.

摘要翻译： 一种功率半导体器件及其制造方法。 功率半导体器件具有至少一个功率半导体芯片，其在其顶侧和其后侧具有大面积电极。 电极通过连接元件与外部触点电连接，功率半导体芯片和连接元件嵌入塑料封装中。 该塑料包装具有多个塑料层，它们一个被压在另一个之上并具有平面平行的上侧。 连接元件布置在至少一个平面平行的上侧，在塑料层之间压迫的层之间，作为图案化的金属层，并且通过接触通孔与外部触点电连接 塑料层中的至少一层。

公开(公告)号：US07759163B2

公开(公告)日：2010-07-20

申请号：US12105837

申请日：2008-04-18

申请人： Werner Kroeninger ,  Josef Schwaiger ,  Ludwig Schneider ,  Ottmar Geitner ,  Markus Brunnbauer ,  Thorsten Meyer ,  Ralf Otremba ,  Josef Hoeglauer ,  Helmut Strack ,  Xaver Schloegel

发明人： Werner Kroeninger ,  Josef Schwaiger ,  Ludwig Schneider ,  Ottmar Geitner ,  Markus Brunnbauer ,  Thorsten Meyer ,  Ralf Otremba ,  Josef Hoeglauer ,  Helmut Strack ,  Xaver Schloegel

IPC分类号： H01L21/00 ,  H01L23/48

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/25 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/072 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/73153 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82102 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor module. One embodiment provides at least two semiconductor chips placed on a carrier. The at least two semiconductor chips are then covered with a molding material to form a molded body. The molded body is thinned until the at least two semiconductor chips are exposed. Then, the carrier is removed from the at least two semiconductor chips. The at least two semiconductor chips are singulated.

摘要翻译： 半导体模块。 一个实施例提供放置在载体上的至少两个半导体芯片。 然后将至少两个半导体芯片用模制材料覆盖以形成模制体。 成型体变薄，直到暴露出至少两个半导体芯片。 然后，从至少两个半导体芯片移除载体。 将至少两个半导体芯片分割。

公开(公告)号：US20090298270A1

公开(公告)日：2009-12-03

申请号：US12474464

申请日：2009-05-29

申请人： Anton Mauder ,  Hans-Joachim Schulze ,  Helmut Strack ,  Hans-Joerg Timme ,  Wolfgang Werner

发明人： Anton Mauder ,  Hans-Joachim Schulze ,  Helmut Strack ,  Hans-Joerg Timme ,  Wolfgang Werner

IPC分类号： H01L21/265

CPC分类号： H01L21/26513 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/3242

摘要： A method for producing a semiconductor is disclosed. One embodiment provides a p-doped semiconductor body having a first side and a second side. An n-doped zone is formed in the semiconductor body by implantation of protons into the semiconductor body via the first side down to a specific depth of the semiconductor body and by subsequent heating at least of the proton-implanted region of the semiconductor body. A pn junction arises in the semiconductor body. The second side of the semiconductor body is removed at least as far as a space charge zone spanned at the pn junction.

摘要翻译： 公开了半导体的制造方法。 一个实施例提供了具有第一侧和第二侧的p掺杂半导体本体。 通过将半导体本体中的质子经由第一侧向下注入到半导体本体的特定深度并且随后至少加热半导体本体的质子注入区域，在半导体本体中形成n掺杂区。 在半导体体中产生pn结。 半导体主体的第二面至少与在pn结处跨过的空间电荷区域一样被去除。

公开(公告)号：US20060244060A1

公开(公告)日：2006-11-02

申请号：US11455397

申请日：2006-06-19

申请人： Holger Kapels ,  Anton Mauder ,  Hans-Joachim Schulze ,  Helmut Strack ,  Jenoe Tihanyi

发明人： Holger Kapels ,  Anton Mauder ,  Hans-Joachim Schulze ,  Helmut Strack ,  Jenoe Tihanyi

IPC分类号： H01L29/76

CPC分类号： H01L29/7805 ,  H01L21/28512 ,  H01L21/28568 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/32 ,  H01L29/456 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/8613

摘要： The present invention relates to a metal-semiconductor contact comprising a semiconductor layer and comprising a metallization applied to the semiconductor layer, a high dopant concentration being introduced into the semiconductor layer such that a non-reactive metal-semiconductor contact is formed between the metallization and the semiconductor layer. The metallization and/or the semiconductor layer are formed in such a way that only a fraction of the introduced doping concentration is electrically active, and a semiconductor layer doped only with this fraction of the doping concentration only forms a Schottky contact when contact is made with the metallization. Furthermore, the invention relates to a semiconductor component comprising a drain zone, body zones embedded therein and source zones again embedded therein. The semiconductor component has metal-semiconductor contacts in which the contacts made contact only with the source zones but not with the body zones.

公开(公告)号：US07087981B2

公开(公告)日：2006-08-08

申请号：US10419597

申请日：2003-04-21

申请人： Holger Kapels ,  Anton Mauder ,  Hans-Joachim Schulze ,  Helmut Strack ,  Jenoe Tihanyi

发明人： Holger Kapels ,  Anton Mauder ,  Hans-Joachim Schulze ,  Helmut Strack ,  Jenoe Tihanyi

IPC分类号： H01L29/207

CPC分类号： H01L29/7805 ,  H01L21/28512 ,  H01L21/28568 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/32 ,  H01L29/456 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/8613

摘要： The present invention relates to a metal-semiconductor contact comprising a semiconductor layer and comprising a metallization applied to the semiconductor layer, a high dopant concentration being introduced into the semiconductor layer such that a non-reactive metal-semiconductor contact is formed between the metallization and the semiconductor layer. The metallization and/or the semiconductor layer are formed in such a way that only a fraction of the introduced doping concentration is electrically active, and a semiconductor layer doped only with this fraction of the doping concentration only forms a Schottky contact when contact is made with the metallization. Furthermore, the invention relates to a semiconductor component comprising a drain zone, body zones embedded therein and source zones again embedded therein. The semiconductor component has metal-semiconductor contacts in which the contacts made contact only with the source zones but not with the body zones.

摘要翻译： 本发明涉及包含半导体层并包含施加到半导体层的金属化的金属 - 半导体接触，将高掺杂浓度引入到半导体层中，使得在金属化和金属化之间形成非反应性金属 - 半导体接触 半导体层。 金属化和/或半导体层以这样的方式形成，使得只有一部分引入的掺杂浓度是电活性的，并且仅当这一部分掺杂浓度掺杂的半导体层仅在与...接触时形成肖特基接触 金属化。 此外，本发明涉及一种半导体部件，其包括漏区，嵌入其中的主体区和再次嵌入其中的源区。 半导体部件具有金属半导体触点，触点仅与源极区域接触而不与主体区域接触。