Apparatus for low power ternary logic circuit

    公开(公告)号:US11817858B2

    公开(公告)日:2023-11-14

    申请号:US17175570

    申请日:2021-02-12

    CPC classification number: H03K19/0013 H10K10/462 G06F2119/06

    Abstract: A static ternary gate is disclosed. The static ternary gate includes a drain-ground path configured to output a drain voltage through a first transistor when a first pull-up circuit is turned on, and output a ground voltage through a second transistor when a first pull-down circuit is turned on, a half-drain path configured to output a half-drain voltage through the first transistor and the second transistor when both a second pull-up circuit and a second pull-down circuit are turned on. The first transistor is configured to connect a node between the first pull-up circuit and the second pull-down circuit to an output terminal, and the second transistor is configured to connect a node between the second pull-up circuit and the first pull-down circuit to the output terminal.

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