公开(公告)号：US11923373B2

公开(公告)日：2024-03-05

申请号：US17502026

申请日：2021-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo Tao ,  Li Wang ,  Ching-Yang Wen ,  Purakh Raj Verma ,  Zhibiao Zhou ,  Dong Yin ,  Gang Ren ,  Jian Xie

IPC: H01L27/12 ,  G11C17/16 ,  H01L23/525 ,  H10B20/20 ,  H10B20/25

CPC classification number: H01L27/1207 ,  G11C17/16 ,  G11C17/165 ,  H01L23/5252 ,  H10B20/20 ,  H10B20/25

Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.

公开(公告)号：US20240074209A1

公开(公告)日：2024-02-29

申请号：US18500994

申请日：2023-11-02

Applicant: UNITED MICROELECTRONICS CORP

Inventor： Jia-Rong Wu ,  I-Fan Chang ,  Rai-Min Huang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/34 ,  H01L23/5226 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.

公开(公告)号：US20240072153A1

公开(公告)日：2024-02-29

申请号：US18506101

申请日：2023-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Hsun-Wen Wang

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66431 ,  H01L29/7786

Abstract: A method for forming a high electron mobility transistor includes the steps of providing a substrate, forming a channel layer, a barrier layer, and a first passivation layer sequentially on the substrate, forming a plurality of trenches through at least a portion of the first passivation layer, forming a second passivation layer on the first passivation layer and covering along sidewalls and bottom surfaces of the trenches, and forming a conductive plate structure on the second passivation layer and filling the trenches.

公开(公告)号：US20240072129A1

公开(公告)日：2024-02-29

申请号：US18504165

申请日：2023-11-08

Applicant: United Microelectronics Corp.

Inventor： Chih-Jung Chen ,  Yu-Jen Yeh

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/40114 ,  H01L21/76224 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/788 ,  H01L21/31051

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

公开(公告)号：US20240072126A1

公开(公告)日：2024-02-29

申请号：US17952298

申请日：2022-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/401 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, performing an ion implantation process to form a hole injection buffer layer (HIBL) on the p-type semiconductor layer, and then forming a gate electrode on the HIBL.

公开(公告)号：US20240071818A1

公开(公告)日：2024-02-29

申请号：US17950120

申请日：2022-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Wei Chi ,  Te-Chang Hsu ,  Yao-Jhan Wang ,  Meng-Yun Wu ,  Chun-Jen Huang

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/76829 ,  H01L21/02041 ,  H01L21/02293 ,  H01L21/02529 ,  H01L21/02532 ,  H01L29/66795

Abstract: A semiconductor device and method of fabricating the same include a substrate, a first epitaxial layer, a first protection layer, and a contact etching stop layer. The substrate includes a PMOS transistor region, and the first epitaxial layer is disposed on the substrate, within the PMOS transistor region. The first protection layer is disposed on the first epitaxial layer, covering surfaces of the first epitaxial layer. The contact etching stop layer is disposed on the first protection layer and the substrate, wherein a portion of the first protection layer is exposed from the contact etching stop layer.

公开(公告)号：US11917836B2

公开(公告)日：2024-02-27

申请号：US17513851

申请日：2021-10-28

Applicant: United Microelectronics Corp.

Inventor： Zong-Han Lin

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10B63/30 ,  H10N70/841 ,  H10N70/8833

Abstract: The invention provides a RRAM structure, which includes a substrate, a high voltage transistor, and a RRAM cell. The high voltage transistor includes a drift region, a gate structure, a source region, a drain region, and an isolation structure. The drift region is located in the substrate. The gate structure is located on the substrate and on a portion of the drift region. The source region and the drain region are located in the substrate on two sides of the gate structure. The drain region is located in the drift region. The isolation structure is located in the drift region and between the gate structure and the drain region. The RRAM cell includes a first electrode, a resistive switching layer, and a second electrode sequentially located on the drain region. The RRAM cell is electrically connected to the high voltage transistor.

公开(公告)号：US11916075B2

公开(公告)日：2024-02-27

申请号：US17741123

申请日：2022-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Yung-Chien Kung ,  Ming-Tsung Yeh ,  Yan-Hsiu Liu ,  Am-Tay Luy ,  Yao-Pi Hsu ,  Ji-Fu Kung

IPC: H01L29/423 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/761 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L21/823481 ,  H01L21/823892 ,  H01L29/7813

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

公开(公告)号：US20240063774A1

公开(公告)日：2024-02-22

申请号：US18499222

申请日：2023-11-01

Applicant: United Microelectronics Corp.

Inventor： Chen-Hsiao Wang ,  Kai-Kuang Ho

IPC: H03H9/10 ,  H03H3/08 ,  H03H9/25 ,  H03H9/02 ,  H10N30/02 ,  H10N30/88

CPC classification number: H03H9/1092 ,  H03H3/08 ,  H03H9/25 ,  H03H9/02937 ,  H10N30/02 ,  H10N30/883 ,  Y10T29/49005 ,  Y10T29/42

Abstract: A surface acoustic wave (SAW) device including a substrate is provided. Multiple surface acoustic wave elements are disposed on the substrate. A conductive surrounding structure includes: a wall part, disposed on the substrate and surrounding the surface acoustic wave elements; and a lateral layer part, disposed on the wall part. The lateral layer part has an opening above the surface acoustic wave elements. A cap layer covers the lateral layer part and closes the opening.

公开(公告)号：US20240057488A1

公开(公告)日：2024-02-15

申请号：US18382055

申请日：2023-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/841 ,  H10B63/845 ,  H10N70/021 ,  H10N70/066 ,  H10N70/8833

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.