-
公开(公告)号:US12082513B2
公开(公告)日:2024-09-03
申请号:US17480694
申请日:2021-09-21
Applicant: Micron Technology, Inc.
Inventor: Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
CPC classification number: H10N70/8416 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C13/0097 , H10B63/80 , H10N70/011 , H10N70/063 , H10N70/231 , H10N70/24 , H10N70/826 , H10N70/8418 , H10N70/882 , H10N70/8822 , H10N70/8825 , H10N70/8828 , G11C2013/0045 , G11C2013/005 , G11C2013/0078 , G11C2013/009 , G11C2013/0092 , G11C2213/13 , G11C2213/52 , G11C2213/73
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
-
162.
公开(公告)号:US20240074168A1
公开(公告)日:2024-02-29
申请号:US17898232
申请日:2022-08-29
Applicant: Micron Technology, Inc.
Inventor: Paolo Fantini , Lorenzo Fratin , Fabio Pellizzer
IPC: H01L27/112
CPC classification number: H01L27/11206
Abstract: Memory devices, and associated systems and methods, are disclosed herein. A representative memory device comprises a substrate, an insulative layer over the substrate, and a memory array over the insulative layer. The memory device further comprises a fuse array positioned in the insulative layer and configured as a non-volatile memory that can store trimming and/or other factors. The fuse array can comprise a plurality of transistors configured as fuses and each including a source, a drain, and a gate. The transistors in a first subset of the transistors have a first resistance across one of the source, the drain, and the gate that represents a first logic state, and the transistors in a second subset of the transistors can have a second resistance across the one of the source, the drain, and the gate that is greater than the first resistance and that represents a second logic state.
-
公开(公告)号:US11848051B2
公开(公告)日:2023-12-19
申请号:US17950630
申请日:2022-09-22
Applicant: Micron Technology, Inc.
Inventor: Fabio Pellizzer
CPC classification number: G11C13/0069 , G11C13/003 , G11C13/0004 , G11C13/0028 , G11C13/0097 , G11C2013/0078
Abstract: Methods, systems, and devices for parallel drift cancellation are described. In some instances, during a first duration, a first voltage may be applied to a word line to threshold one or more memory cells included in a first subset of memory cells. During a second duration, a second voltage may be applied to the word line to write a first logic state to one or more memory cells included in the first subset and to threshold one or more memory cells included in a second subset of memory cells. During a third duration, a third voltage may be applied to the word line to write a second logic state to one or more memory cells included in the second subset of memory cells.
-
公开(公告)号:US11798620B2
公开(公告)日:2023-10-24
申请号:US17816612
申请日:2022-08-01
Applicant: Micron Technology, Inc.
Inventor: Innocenzo Tortorelli , Russell L. Meyer , Agostino Pirovano , Andrea Redaelli , Lorenzo Fratin , Fabio Pellizzer
CPC classification number: G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/005 , G11C2013/0052 , G11C2013/0073 , G11C2013/0092 , G11C2213/71 , G11C2213/76
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
-
公开(公告)号:US11790987B2
公开(公告)日:2023-10-17
申请号:US17874965
申请日:2022-07-27
Applicant: Micron Technology, Inc.
Inventor: Lorenzo Fratin , Paolo Fantini , Fabio Pellizzer , Thomas M. Graettinger
CPC classification number: G11C13/0023 , G11C13/003 , G11C13/0004
Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder of a memory device may include transistors in a first layer between a memory array and a second layer that includes one or more components associated with the memory array. The second layer may include CMOS pre-decoding circuitry, among other components. The decoder may include CMOS transistors in the first layer. The CMOS transistors may control which voltage source is coupled with an access line based on a gate voltage applied to a p-type transistor and a n-type transistor. For example, a first gate voltage applied to a p-type transistor may couple a source node with the access line and bias the access line to a source voltage. A second gate voltage applied to the n-type transistor may couple a ground node with the access line and bias the access line to a ground voltage.
-
公开(公告)号:US11729999B2
公开(公告)日:2023-08-15
申请号:US17735810
申请日:2022-05-03
Applicant: Micron Technology, Inc.
Inventor: Innocenzo Tortorelli , Fabio Pellizzer
CPC classification number: H10B63/845 , G11C13/003 , G11C13/0004 , H10B63/34 , H10N70/231 , G11C2213/71 , G11C2213/75
Abstract: Methods, systems, and devices for a capacitive pillar architecture for a memory array are described. An access line within a memory array may be, include, or be coupled with a pillar. The pillar may include an exterior electrode, such as a hollow exterior electrode, surrounding an inner dielectric material that may further surround an interior, core electrode. The interior electrode may be maintained at a voltage level during at least a portion of an access operation for a memory cell coupled with the pillar. Such a pillar structure may increase a capacitance of the pillar, for example, based on a capacitive coupling between the interior and exterior electrodes. The increased capacitance may provide benefits associated with operating the memory array, such as increased memory cell programming speed, programming reliability, and read disturb immunity.
-
公开(公告)号:US20230207002A1
公开(公告)日:2023-06-29
申请号:US17647578
申请日:2022-01-10
Applicant: Micron Technology, Inc.
Inventor: Innocenzo Tortorelli , Fabio Pellizzer , Mattia Robustelli , Alessandro Sebastiani
IPC: G11C13/00
CPC classification number: G11C13/003 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2213/71
Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.
-
公开(公告)号:US11688460B2
公开(公告)日:2023-06-27
申请号:US17491070
申请日:2021-09-30
Applicant: Micron Technology, Inc.
Inventor: Fabio Pellizzer , Nevil N. Gajera , John Frederic Schreck
IPC: G11C13/00
CPC classification number: G11C13/0026 , G11C13/003 , G11C13/0004 , G11C13/0028
Abstract: As described, an apparatus may include a memory cell corresponding to a memory address and an access line forming at least a portion of the memory cell. The apparatus may include a first decoder associated with a first delivery driver coupled to a first end of the access line and a second decoder associated with a second delivery driver coupled to another end of the access line.
-
公开(公告)号:US11664073B2
公开(公告)日:2023-05-30
申请号:US17221412
申请日:2021-04-02
Applicant: Micron Technology, Inc.
Inventor: Karthik Sarpatwari , Fabio Pellizzer , Nevil N. Gajera
CPC classification number: G11C16/10 , G06F11/1076 , G06N3/04 , G06N3/08 , G11C11/56 , G11C16/0483
Abstract: Systems, methods and apparatus to determine, in response to a command to write data into a set of memory cells, a programming mode of a set of memory cell to optimize performance in retrieving the data back from the set of memory cells. For example, based on usages of a memory region containing the memory cell set, a predictive model can be used to identify a combination of an amount of redundant information to be stored into the memory cells in the set and a programming mode of the memory cells to store the redundant information. Increasing the amount of redundant information can increase error recovery capability but increase bit error rate and/or increase time to read. The predictive model is trained to predict the combination to optimize read performance.
-
公开(公告)号:US11616098B2
公开(公告)日:2023-03-28
申请号:US17833596
申请日:2022-06-06
Applicant: Micron Technology, Inc.
Inventor: Lingming Yang , Karthik Sarpatwari , Fabio Pellizzer , Nevil N. Gajera , Lei Wei
IPC: H01L27/24 , H01L23/528 , H01L45/00 , H01L23/532
Abstract: An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.
-
-
-
-
-
-
-
-
-