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    MEMORY DEVICES HAVING ONE-TIME-PROGRAMMABLE FUSES AND/OR ANTIFUSES FORMED FROM THIN-FILM TRANSISTORS
    162.
    发明公开
    MEMORY DEVICES HAVING ONE-TIME-PROGRAMMABLE FUSES AND/OR ANTIFUSES FORMED FROM THIN-FILM TRANSISTORS 审中-公开

    公开(公告)号：US20240074168A1

    公开(公告)日：2024-02-29

    申请号：US17898232

    申请日：2022-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Fantini ,  Lorenzo Fratin ,  Fabio Pellizzer

    IPC: H01L27/112

    CPC classification number: H01L27/11206

    Abstract: Memory devices, and associated systems and methods, are disclosed herein. A representative memory device comprises a substrate, an insulative layer over the substrate, and a memory array over the insulative layer. The memory device further comprises a fuse array positioned in the insulative layer and configured as a non-volatile memory that can store trimming and/or other factors. The fuse array can comprise a plurality of transistors configured as fuses and each including a source, a drain, and a gate. The transistors in a first subset of the transistors have a first resistance across one of the source, the drain, and the gate that represents a first logic state, and the transistors in a second subset of the transistors can have a second resistance across the one of the source, the drain, and the gate that is greater than the first resistance and that represents a second logic state.

    Parallel drift cancellation
    163.
    发明授权
    Parallel drift cancellation 有权

    公开(公告)号：US11848051B2

    公开(公告)日：2023-12-19

    申请号：US17950630

    申请日：2022-09-22

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/003 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0097 ,  G11C2013/0078

    Abstract: Methods, systems, and devices for parallel drift cancellation are described. In some instances, during a first duration, a first voltage may be applied to a word line to threshold one or more memory cells included in a first subset of memory cells. During a second duration, a second voltage may be applied to the word line to write a first logic state to one or more memory cells included in the first subset and to threshold one or more memory cells included in a second subset of memory cells. During a third duration, a third voltage may be applied to the word line to write a second logic state to one or more memory cells included in the second subset of memory cells.

    Decoding for a memory device
    165.
    发明授权
    Decoding for a memory device 有权

    公开(公告)号：US11790987B2

    公开(公告)日：2023-10-17

    申请号：US17874965

    申请日：2022-07-27

    Applicant: Micron Technology, Inc.

    Inventor： Lorenzo Fratin ,  Paolo Fantini ,  Fabio Pellizzer ,  Thomas M. Graettinger

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/0023 ,  G11C13/003 ,  G11C13/0004

    Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder of a memory device may include transistors in a first layer between a memory array and a second layer that includes one or more components associated with the memory array. The second layer may include CMOS pre-decoding circuitry, among other components. The decoder may include CMOS transistors in the first layer. The CMOS transistors may control which voltage source is coupled with an access line based on a gate voltage applied to a p-type transistor and a n-type transistor. For example, a first gate voltage applied to a p-type transistor may couple a source node with the access line and bias the access line to a source voltage. A second gate voltage applied to the n-type transistor may couple a ground node with the access line and bias the access line to a ground voltage.

    Capacitive pillar architecture for a memory array
    166.
    发明授权
    Capacitive pillar architecture for a memory array 有权

    公开(公告)号：US11729999B2

    公开(公告)日：2023-08-15

    申请号：US17735810

    申请日：2022-05-03

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer

    IPC: G11C13/00 ,  H10B63/00 ,  H10N70/20

    CPC classification number: H10B63/845 ,  G11C13/003 ,  G11C13/0004 ,  H10B63/34 ,  H10N70/231 ,  G11C2213/71 ,  G11C2213/75

    Abstract: Methods, systems, and devices for a capacitive pillar architecture for a memory array are described. An access line within a memory array may be, include, or be coupled with a pillar. The pillar may include an exterior electrode, such as a hollow exterior electrode, surrounding an inner dielectric material that may further surround an interior, core electrode. The interior electrode may be maintained at a voltage level during at least a portion of an access operation for a memory cell coupled with the pillar. Such a pillar structure may increase a capacitance of the pillar, for example, based on a capacitive coupling between the interior and exterior electrodes. The increased capacitance may provide benefits associated with operating the memory array, such as increased memory cell programming speed, programming reliability, and read disturb immunity.

    CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS
    167.
    发明公开
    CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS 审中-公开

    公开(公告)号：US20230207002A1

    公开(公告)日：2023-06-29

    申请号：US17647578

    申请日：2022-01-10

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Mattia Robustelli ,  Alessandro Sebastiani

    IPC: G11C13/00

    CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71

    Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.

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