公开(公告)号：US20160013291A1

公开(公告)日：2016-01-14

申请号：US14859729

申请日：2015-09-21

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3213 ,  H01L29/161 ,  H01L21/31

CPC classification number: H01L29/6681 ,  H01L21/30604 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A fin structure is formed in and above a substrate and includes a portion of a substrate semiconductor material, a first epi semiconductor material formed above the substrate semiconductor material portion, and a second epi semiconductor material formed above the first epi semiconductor material. A sacrificial gate structure is formed above the fin structure, a sidewall spacer is formed adjacent the sacrificial gate structure, and at least one etching process is performed to remove portions of the fin structure positioned laterally outside of the sidewall spacer so as to define a fin cavity source/drain regions and to expose edges of the fin structure positioned under the spacer. An epi etch stop layer is formed on the exposed edges of the fin structure and within the fin cavity, and the first epi semiconductor material is removed selectively from the fin structure so as to form a channel cavity therein.

Abstract translation: 鳍状结构形成在基板的上方，上方形成有基板半导体材料的一部分，形成在基板半导体材料部分的上方的第一外延半导体材料，以及形成在第一外延半导体材料的上方的第二外延半导体材料。 牺牲栅极结构形成在翅片结构的上方，邻近牺牲栅极结构形成侧壁间隔物，并且执行至少一个蚀刻工艺以去除位于侧壁间隔物外侧的翅片结构的部分，从而限定翅片 空腔源极/漏极区域并且暴露位于间隔物下方的鳍结构的边缘。 在翅片结构的暴露边缘和翅片腔内形成外延蚀刻停止层，并且第一外延半导体材料被选择性地从翅片结构移除，以在其中形成沟槽。

公开(公告)号：US09236380B2

公开(公告)日：2016-01-12

申请号：US14050576

申请日：2013-10-10

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Qing Liu ,  Nicolas Loubet

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161

Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.

Abstract translation: 制造半导体器件的方法可以包括在绝缘体上半导体（SOI）晶片的第一半导体层上形成第二半导体层，该第二半导体层包括与第一半导体层的第一半导体材料不同的第二半导体材料。 该方法还可以包括在非氧化性气氛中进行热处理，以将第二半导体材料扩散到第一半导体层中，以及去除第二半导体层。

公开(公告)号：US09230991B2

公开(公告)日：2016-01-05

申请号：US14253904

申请日：2014-04-16

Applicant: STMicroelectronics, Inc. ,  Commissariat á l'Énergie Atomique et aux Énergies Alternatives

Inventor： Nicolas Loubet ,  Sylvain Maitrejean ,  Romain Wacquez

IPC: H01L23/48 ,  H01L27/12 ,  H01L21/84 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02 ,  H01L21/266 ,  H01L21/306

CPC classification number: H01L21/845 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/7849

Abstract: Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently.

Abstract translation: 描述了在衬底上的半导体层中形成局部的，不同应变的区域的方法和结构。 可以对原始半导体层中的初始的，无约束的绝缘体上半导体衬底进行处理以形成不同应变的区域。 不同应变区域可能具有相反类型的应变。 不同区域中的菌株可以独立形成。

公开(公告)号：US09166023B2

公开(公告)日：2015-10-20

申请号：US13964009

申请日：2013-08-09

Applicant: STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Jin Cho

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: Methods and structures for forming fully insulated finFETs beginning with a bulk semiconductor substrate are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first epitaxial layer may be sacrificial. A final gate structure may be formed around the fin structures, and the first epitaxial layer removed to form a void between a fin and the substrate. The void may be filled with an insulator to fully insulate the fin.

Abstract translation: 描述了以体半导体衬底开始形成完全绝缘的finFET的方法和结构。 用于finFET的鳍结构可以形成在生长在块状衬底上的两个外延层中。 第一外延层可以是牺牲的。 可以在翅片结构周围形成最终的栅极结构，并且去除第一外延层以在翅片和衬底之间形成空隙。 空隙可以填充绝缘体以使翅片完全绝缘。

公开(公告)号：US09105663B1

公开(公告)日：2015-08-11

申请号：US14168175

申请日：2014-01-30

Applicant: International Business Machines Corporation ,  Renesas Electronics Corporation ,  STMicroelectronics, Inc.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Nicolas Loubet ,  Shogo Mochizuki ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Chun-Chen Yeh

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/225 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/2254 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/7841 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure generally provides for a method of forming a FinFET with a silicon germanium (SiGe) stressor, in addition to a FinFET structure obtained from embodiments of the method. The method can include forming a semiconductor fin on a buried insulator layer; forming a gate structure on the semiconductor fin; forming a silicon germanium (SiGe) layer on the buried insulator layer, wherein the SiGe layer contacts the semiconductor fin; and heating the SiGe layer, wherein the heating diffuses germanium (Ge) into the semiconductor fin.

Abstract translation: 本公开通常提供了除了由该方法的实施例获得的FinFET结构之外还形成具有硅锗（SiGe）应力源的FinFET的方法。 该方法可以包括在掩埋绝缘体层上形成半导体鳍片; 在半导体鳍片上形成栅极结构; 在所述掩埋绝缘体层上形成硅锗层（SiGe），其中所述SiGe层接触所述半导体鳍片; 并加热SiGe层，其中加热使锗（Ge）扩散到半导体鳍片中。

公开(公告)号：US09093496B2

公开(公告)日：2015-07-28

申请号：US13945445

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Ajey P. Jacob ,  Kangguo Cheng ,  Bruce B. Doris ,  Nicolas Loubet ,  Prasanna Khare ,  Ramachandra Divakaruni

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/088 ,  H01L27/105 ,  H01L29/78 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L21/302

CPC classification number: H01L21/76243 ,  H01L21/302 ,  H01L21/76267 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/105 ,  H01L27/1211 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor fabrication methods are provided which include facilitating fabricating semiconductor fin structures by: providing a wafer with at least one fin extending above a substrate, the at least one fin including a first layer disposed above a second layer; mechanically stabilizing the first layer; removing at least a portion of the second layer of the fin(s) to create a void below the first layer; filling the void, at least partially, below the first layer with an isolation material to create an isolation layer within the fin(s); and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the fin(s), and a fin device(s) of a second architectural type in a second fin region of the fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供半导体制造方法，其包括通过以下方式制造半导体鳍片结构：提供具有在衬底上延伸的至少一个翅片的晶片，所述至少一个鳍片包括设置在第二层上方的第一层; 机械稳定第一层; 去除所述翅片的所述第二层的至少一部分以在所述第一层下面形成空隙; 至少部分地用隔离材料填充第一层下面的空隙，以在散热片内产生隔离层; 并且在翅片的第一翅片区域中形成第一结构类型的翅片装置，并且在翅片的第二翅片区域中形成第二结构类型的翅片装置， ，其中第一种架构类型和第二种架构类型是不同的鳍设备架构。

公开(公告)号：US20150162433A1

公开(公告)日：2015-06-11

申请号：US14097565

申请日：2013-12-05

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Stephane Monfray ,  Ronald Kevin Sampson

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either SOI or bulk type). Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

Abstract translation: 第一半导体材料的细长散热片与下层基底层（SOI或本体型）绝缘和形成。 然后形成第二半导体材料的细长的栅极，以在沟道区域上跨过细长的翅片，并且栅极侧壁被侧壁间隔物覆盖。 提供保护材料以覆盖下面的基底层并且在细长门之间限定细长翅片的侧壁上的侧壁间隔物。 位于保护材料侧壁间隔件（但不在细长门下）的细长翅片的第一半导体材料和绝缘材料被去除以形成与沟道区域对准的沟槽。 然后在细长门之间的每个沟槽内外延生长另外的半导体材料，以形成邻近由位于细长栅极下方的第一半导体材料的细长鳍片形成的沟道区域的源极 - 漏极区域。

公开(公告)号：US20150162248A1

公开(公告)日：2015-06-11

申请号：US14097556

申请日：2013-12-05

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L21/84 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/76205 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795

Abstract: On a substrate formed of a first semiconductor material, a first overlying layer formed of a second semiconductor material is deposited. A second overlying layer formed of a third semiconductor material is deposited over the first overlying layer. The first and second overlying layers are patterned to define fins, wherein each fin includes a first region formed of the third material over a second region formed of the second material. An oxide material fills the space between the fins. A thermal oxidation is then performed to convert the second region to a material insulating the first region formed of the third material from the substrate. As an optional step, the second region formed of the second material is horizontally thinned before the oxide material is deposited and the thermal oxidation is performed. Once the fins are formed and insulated from the substrate, conventional FinFET fabrication is performed.

Abstract translation: 在由第一半导体材料形成的衬底上沉积由第二半导体材料形成的第一覆盖层。 由第三半导体材料形成的第二覆盖层沉积在第一覆盖层上。 图案化第一和第二覆盖层以限定翅片，其中每个翅片包括在由第二材料形成的第二区域上由第三材料形成的第一区域。 氧化物填充翅片之间的空间。 然后进行热氧化以将第二区域转换为将由第三材料形成的第一区域与衬底绝缘的材料。 作为可选步骤，在沉积氧化物材料并进行热氧化之前，由第二材料形成的第二区域被水平地薄化。 一旦翅片形成并与衬底绝缘，就进行常规的FinFET制造。

公开(公告)号：US20150099334A1

公开(公告)日：2015-04-09

申请号：US14048263

申请日：2013-10-08

Applicant: STMicroelectronics, Inc.

Inventor： QING LIU ,  Nicolas Loubet

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7849 ,  H01L21/02532 ,  H01L21/2251 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

Abstract translation: 一种用于形成互补金属氧化物半导体（CMOS）半导体器件的方法包括提供包括具有第一和第二横向相邻应力半导体部分的应力半导体层的受应力的绝缘体上硅（sSOI）晶片。 第一应力半导体部分限定第一有源区。 第二应力半导体部分被未受应力的半导体部分代替。 未受应力的半导体部分包括第一半导体材料。 该方法还包括将第二半导体材料驱动到限定第二有源区的无应力半导体部分的第一半导体材料中。

公开(公告)号：US08956942B2

公开(公告)日：2015-02-17

申请号：US13725528

申请日：2012-12-21

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/0653 ,  H01L21/02532 ,  H01L21/02661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/7848

Abstract: Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel (fin) and the substrate during fabrication of the device. Similarly, source/drain-to-substrate leakage in a FinFET device is prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. Forming such an insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. In an array of semiconducting fins made up of a multi-layer stack, the bottom material is removed, thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material is then filled with oxide to better support the fins and to isolate the array of fins from the substrate.

Abstract translation: 通过在器件的制造期间在半导体沟道（鳍）和衬底之间插入绝缘层来防止FinFET器件中的沟道到衬底泄漏。 类似地，通过在源极/漏极区域和衬底之间插入绝缘层来隔离源极/漏极区域来防止FinFET器件中的源极/漏极到衬底泄漏。 形成这样的绝缘层将物理和电气上的导电路径与衬底隔离，从而防止电流泄漏。 在由多层堆叠构成的半导体鳍阵列中，去除底部材料，从而产生悬浮在硅表面上方的翅片阵列。 然后在剩余的顶部翅片材料下面形成的间隙填充氧化物以更好地支撑翅片并且将翅片阵列与基底隔离开。