公开(公告)号：US20150270398A1

公开(公告)日：2015-09-24

申请号：US14223373

申请日：2014-03-24

Applicant: STMicroelectronics, Inc. ,  Globalfoundries Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/308 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/7848 ,  H01L21/28194 ,  H01L21/3085 ,  H01L29/0847 ,  H01L29/515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, forming a fin structure comprised of a semiconductor material, a first epi semiconductor material and a second epi semiconductor material, forming a sacrificial gate structure above the fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one etching process to remove the portions of the fin structure positioned laterally outside of the sidewall spacer so as to thereby define a fin cavity in the source/drain regions of the device and to expose edges of the fin structure positioned under the sidewall spacer, and performing an epitaxial deposition process to form an epi etch stop layer on the exposed edges of the fin structure positioned under the sidewall spacer and within the fin cavity.

Abstract translation: 所公开的一种方法包括形成由半导体材料，第一外延半导体材料和第二外延半导体材料构成的鳍状结构，在鳍状结构之上形成牺牲栅极结构，形成邻近牺牲栅极结构的侧壁间隔物 执行至少一个蚀刻工艺以去除位于侧壁间隔件外侧的翅片结构的部分，从而在该装置的源极/漏极区域中限定翅片空腔并且暴露位于该侧壁间隔之下的翅片结构的边缘 并且执行外延沉积工艺以在位于侧壁间隔件下方和翅片腔内的翅片结构的暴露边缘上形成外延蚀刻停止层。

公开(公告)号：US09466664B2

公开(公告)日：2016-10-11

申请号：US14982474

申请日：2015-12-29

Applicant: STMicroelectronics, Inc. ,  Commissariat a l'energie Atomique et Aux Energies Alternatives ,  GlobalFoundries Inc.

Inventor： Pierre Morin ,  Maud Vinet ,  Laurent Grenouillet ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/283 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/0607 ,  H01L21/02636 ,  H01L21/283 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/1066 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

Abstract translation: 描述了从双轴应变半导体层形成单轴应变纳米级半导体条的方法和结构。 可以使用空间双倍的心轴工艺来形成用于图案化通过双轴应变半导体层的致密的窄沟槽的掩模。 所得到的双轴应变层的切片增强了载流子迁移率并且可以提高器件性能。

公开(公告)号：US09349730B2

公开(公告)日：2016-05-24

申请号：US13945415

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Ajey Poovannummoottil Jacob ,  Kangguo Cheng ,  Bruce B. Doris ,  Nicolas Loubet ,  Prasanna Khare ,  Ramachandra Divakaruni

IPC: H01L21/20 ,  H01L27/088 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供了由这些方法形成的方法和半导体结构，其有助于制造半导体鳍结构。 所述方法包括例如：提供具有在衬底上延伸的至少一个半导体鳍片的晶片; 将所述半导体鳍片的一部分转换成隔离层，所述隔离层将所述半导体鳍片的半导体层与所述衬底分离; 并且在半导体鳍片的第一鳍片区域中形成第一结构类型的翅片装置，并且在半导体鳍片的第二鳍片区域中形成第二结构类型的鳍片装置（ s），其中第一架构类型和第二架构类型是不同的fin设备架构。

公开(公告)号：US20160093739A1

公开(公告)日：2016-03-31

申请号：US14963683

申请日：2015-12-09

Applicant: STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L21/28194 ,  H01L21/3085 ,  H01L29/0847 ,  H01L29/515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: A FinFET device includes a fin structure positioned in the channel region of the device and a gate structure positioned above the fin structure, wherein the fin structure includes a portion of a semiconductor substrate and an epi semiconductor material positioned vertically above the portion of the semiconductor substrate. Sidewall spacers are positioned adjacent the gate structure and a fin cavity is positioned in source/drain regions of the device, wherein the fin structure has edges in a gate width direction that are substantially self-aligned with the sidewall spacers and the semiconductor substrate defines the bottom of the fin cavity. A silicon etch stop layer is positioned on and in contact with the edges of the fin structure and within the fin cavity, and a stressed semiconductor material is positioned on and in contact with the silicon etch stop layer and at least partially within the fin cavity.

Abstract translation: FinFET器件包括位于器件的沟道区域中的鳍结构和位于鳍结构上方的栅极结构，其中鳍结构包括半导体衬底的一部分和位于半导体衬底的部分上方的外延半导体材料 。 侧壁间隔件位于栅极结构附近并且翅片空腔位于器件的源极/漏极区域中，其中鳍状结构具有栅极宽度方向上的边缘，其基本上与侧壁间隔物自对准，并且半导体衬底限定 翅片底部底部。 硅蚀刻停止层定位在翅片结构的边缘并且在翅片空腔内并与其接触，并且应力半导体材料定位在硅蚀刻停止层上并且与硅蚀刻停止层接触并且至少部分地位于翅片腔内。

公开(公告)号：US20160013291A1

公开(公告)日：2016-01-14

申请号：US14859729

申请日：2015-09-21

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3213 ,  H01L29/161 ,  H01L21/31

CPC classification number: H01L29/6681 ,  H01L21/30604 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A fin structure is formed in and above a substrate and includes a portion of a substrate semiconductor material, a first epi semiconductor material formed above the substrate semiconductor material portion, and a second epi semiconductor material formed above the first epi semiconductor material. A sacrificial gate structure is formed above the fin structure, a sidewall spacer is formed adjacent the sacrificial gate structure, and at least one etching process is performed to remove portions of the fin structure positioned laterally outside of the sidewall spacer so as to define a fin cavity source/drain regions and to expose edges of the fin structure positioned under the spacer. An epi etch stop layer is formed on the exposed edges of the fin structure and within the fin cavity, and the first epi semiconductor material is removed selectively from the fin structure so as to form a channel cavity therein.

Abstract translation: 鳍状结构形成在基板的上方，上方形成有基板半导体材料的一部分，形成在基板半导体材料部分的上方的第一外延半导体材料，以及形成在第一外延半导体材料的上方的第二外延半导体材料。 牺牲栅极结构形成在翅片结构的上方，邻近牺牲栅极结构形成侧壁间隔物，并且执行至少一个蚀刻工艺以去除位于侧壁间隔物外侧的翅片结构的部分，从而限定翅片 空腔源极/漏极区域并且暴露位于间隔物下方的鳍结构的边缘。 在翅片结构的暴露边缘和翅片腔内形成外延蚀刻停止层，并且第一外延半导体材料被选择性地从翅片结构移除，以在其中形成沟槽。

公开(公告)号：US09673222B2

公开(公告)日：2017-06-06

申请号：US15156506

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Kangguo Cheng ,  Bruce Doris ,  Nicolas Loubet ,  Prasanna Khare ,  Rama Divakaruni

IPC: H01L27/12 ,  H01L21/02 ,  H01L27/088 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/84 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.

公开(公告)号：US09252208B1

公开(公告)日：2016-02-02

申请号：US14447678

申请日：2014-07-31

Applicant: STMicroelectronics, Inc. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  GLOBALFOUNDRIES Inc.

Inventor： Pierre Morin ,  Maud Vinet ,  Laurent Grenouillet ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/02636 ,  H01L21/283 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/1066 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

公开(公告)号：US20160133692A1

公开(公告)日：2016-05-12

申请号：US14982474

申请日：2015-12-29

Applicant: STMicroelectronics, Inc. ,  Commissariat a I'energie Atomique et Aux Energies Alternatives ,  GlobalFoundries Inc.

Inventor： Pierre Morin ,  Maud Vinet ,  Laurent Grenouillet ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/283 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/02636 ,  H01L21/283 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/1066 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

Abstract translation: 描述了从双轴应变半导体层形成单轴应变纳米级半导体条的方法和结构。 可以使用空间双倍的心轴工艺来形成用于图案化通过双轴应变半导体层的致密的窄沟槽的掩模。 所得到的双轴应变层的切片增强了载流子迁移率并且可以提高器件性能。

公开(公告)号：US09287130B1

公开(公告)日：2016-03-15

申请号：US14676345

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Ruilong Xie ,  Bruce Doris ,  Kangguo Cheng ,  Jason R. Cantone ,  Sylvie Mignot ,  David Moreau ,  Muthumanickam Sankarapandian ,  Pierre Morin ,  Su Chen Fan ,  Kisik Choi ,  Murat K. Akarvardar

IPC: H01L21/00 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L21/823431 ,  H01L21/30604 ,  H01L21/845 ,  H01L29/66795

Abstract: A method includes forming a plurality of fin elements above a substrate. A mask is formed above the substrate. The mask has an opening defined above at least one selected fin element of the plurality of fin elements. An ion species is implanted into the at least one selected fin element through the opening to increase its etch characteristics relative to the other fin elements. The at least one selected fin element is removed selectively relative to the other fin elements.

Abstract translation: 一种方法包括在基底上形成多个翅片元件。 在基板上形成掩模。 掩模具有限定在多个翅片元件中的至少一个选定翅片元件上方的开口。 通过开口将离子物质注入到至少一个选定的翅片元件中，以相对于其它翅片元件增加其蚀刻特性。 选择性地将至少一个选定的翅片元件相对于其它翅片元件移除。

公开(公告)号：US09263580B2

公开(公告)日：2016-02-16

申请号：US14223373

申请日：2014-03-24

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/308 ,  H01L21/28

CPC classification number: H01L29/7848 ,  H01L21/28194 ,  H01L21/3085 ,  H01L29/0847 ,  H01L29/515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, forming a fin structure comprised of a semiconductor material, a first epi semiconductor material and a second epi semiconductor material, forming a sacrificial gate structure above the fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one etching process to remove the portions of the fin structure positioned laterally outside of the sidewall spacer so as to thereby define a fin cavity in the source/drain regions of the device and to expose edges of the fin structure positioned under the sidewall spacer, and performing an epitaxial deposition process to form an epi etch stop layer on the exposed edges of the fin structure positioned under the sidewall spacer and within the fin cavity.

Abstract translation: 所公开的一种方法包括形成由半导体材料，第一外延半导体材料和第二外延半导体材料构成的鳍状结构，在鳍状结构之上形成牺牲栅极结构，形成邻近牺牲栅极结构的侧壁间隔物 执行至少一个蚀刻工艺以去除位于侧壁间隔件外侧的翅片结构的部分，从而在该装置的源极/漏极区域中限定翅片空腔并且暴露位于该侧壁间隔之下的翅片结构的边缘 并且执行外延沉积工艺以在位于侧壁间隔件下方和翅片腔内的翅片结构的暴露边缘上形成外延蚀刻停止层。