公开(公告)号：US09349730B2

公开(公告)日：2016-05-24

申请号：US13945415

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Ajey Poovannummoottil Jacob ,  Kangguo Cheng ,  Bruce B. Doris ,  Nicolas Loubet ,  Prasanna Khare ,  Ramachandra Divakaruni

IPC: H01L21/20 ,  H01L27/088 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供了由这些方法形成的方法和半导体结构，其有助于制造半导体鳍结构。 所述方法包括例如：提供具有在衬底上延伸的至少一个半导体鳍片的晶片; 将所述半导体鳍片的一部分转换成隔离层，所述隔离层将所述半导体鳍片的半导体层与所述衬底分离; 并且在半导体鳍片的第一鳍片区域中形成第一结构类型的翅片装置，并且在半导体鳍片的第二鳍片区域中形成第二结构类型的鳍片装置（ s），其中第一架构类型和第二架构类型是不同的fin设备架构。

公开(公告)号：US09166023B2

公开(公告)日：2015-10-20

申请号：US13964009

申请日：2013-08-09

Applicant: STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Jin Cho

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: Methods and structures for forming fully insulated finFETs beginning with a bulk semiconductor substrate are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first epitaxial layer may be sacrificial. A final gate structure may be formed around the fin structures, and the first epitaxial layer removed to form a void between a fin and the substrate. The void may be filled with an insulator to fully insulate the fin.

Abstract translation: 描述了以体半导体衬底开始形成完全绝缘的finFET的方法和结构。 用于finFET的鳍结构可以形成在生长在块状衬底上的两个外延层中。 第一外延层可以是牺牲的。 可以在翅片结构周围形成最终的栅极结构，并且去除第一外延层以在翅片和衬底之间形成空隙。 空隙可以填充绝缘体以使翅片完全绝缘。

公开(公告)号：US09093496B2

公开(公告)日：2015-07-28

申请号：US13945445

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Ajey P. Jacob ,  Kangguo Cheng ,  Bruce B. Doris ,  Nicolas Loubet ,  Prasanna Khare ,  Ramachandra Divakaruni

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/088 ,  H01L27/105 ,  H01L29/78 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L21/302

CPC classification number: H01L21/76243 ,  H01L21/302 ,  H01L21/76267 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/105 ,  H01L27/1211 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor fabrication methods are provided which include facilitating fabricating semiconductor fin structures by: providing a wafer with at least one fin extending above a substrate, the at least one fin including a first layer disposed above a second layer; mechanically stabilizing the first layer; removing at least a portion of the second layer of the fin(s) to create a void below the first layer; filling the void, at least partially, below the first layer with an isolation material to create an isolation layer within the fin(s); and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the fin(s), and a fin device(s) of a second architectural type in a second fin region of the fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供半导体制造方法，其包括通过以下方式制造半导体鳍片结构：提供具有在衬底上延伸的至少一个翅片的晶片，所述至少一个鳍片包括设置在第二层上方的第一层; 机械稳定第一层; 去除所述翅片的所述第二层的至少一部分以在所述第一层下面形成空隙; 至少部分地用隔离材料填充第一层下面的空隙，以在散热片内产生隔离层; 并且在翅片的第一翅片区域中形成第一结构类型的翅片装置，并且在翅片的第二翅片区域中形成第二结构类型的翅片装置， ，其中第一种架构类型和第二种架构类型是不同的鳍设备架构。

公开(公告)号：US09673222B2

公开(公告)日：2017-06-06

申请号：US15156506

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Kangguo Cheng ,  Bruce Doris ,  Nicolas Loubet ,  Prasanna Khare ,  Rama Divakaruni

IPC: H01L27/12 ,  H01L21/02 ,  H01L27/088 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/84 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.

公开(公告)号：US20150041898A1

公开(公告)日：2015-02-12

申请号：US13964009

申请日：2013-08-09

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Jin Cho

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: Methods and structures for forming fully insulated finFETs beginning with a bulk semiconductor substrate are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first epitaxial layer may be sacrificial. A final gate structure may be formed around the fin structures, and the first epitaxial layer removed to form a void between a fin and the substrate. The void may be filled with an insulator to fully insulate the fin.

Abstract translation: 描述了以体半导体衬底开始形成完全绝缘的finFET的方法和结构。 用于finFET的鳍结构可以形成在生长在块状衬底上的两个外延层中。 第一外延层可以是牺牲的。 可以在翅片结构周围形成最终的栅极结构，并且去除第一外延层以在翅片和衬底之间形成空隙。 空隙可以填充绝缘体以使翅片完全绝缘。

公开(公告)号：US10170475B2

公开(公告)日：2019-01-01

申请号：US15448626

申请日：2017-03-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Stephane Allegret-Maret ,  Kangguo Cheng ,  Bruce Doris ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L27/092 ,  H01L27/11 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/786 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417

Abstract: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.

公开(公告)号：US09893147B2

公开(公告)日：2018-02-13

申请号：US15345250

申请日：2016-11-07

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L27/01 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/16 ,  H01L29/49 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/02532 ,  H01L21/02661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/7848

Abstract: Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel and the substrate during fabrication of the device. Similarly, source/drain-to-substrate leakage in a FinFET device is prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. Forming such an insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. In an array of semiconducting fins made up of a multi-layer stack, the bottom material is removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material is then filled with oxide to better support the fins and to isolate the array of fins from the substrate.

公开(公告)号：US09502292B2

公开(公告)日：2016-11-22

申请号：US14856949

申请日：2015-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/20 ,  H01L21/425 ,  H01L21/768 ,  H01L21/762 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

公开(公告)号：US09099570B2

公开(公告)日：2015-08-04

申请号：US14097556

申请日：2013-12-05

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L27/092 ,  H01L21/84 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L21/845 ,  H01L21/76205 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795

Abstract: On a substrate formed of a first semiconductor material, a first overlying layer formed of a second semiconductor material is deposited. A second overlying layer formed of a third semiconductor material is deposited over the first overlying layer. The first and second overlying layers are patterned to define fins, wherein each fin includes a first region formed of the third material over a second region formed of the second material. An oxide material fills the space between the fins. A thermal oxidation is then performed to convert the second region to a material insulating the first region formed of the third material from the substrate. As an optional step, the second region formed of the second material is horizontally thinned before the oxide material is deposited and the thermal oxidation is performed. Once the fins are formed and insulated from the substrate, conventional FinFET fabrication is performed.

Abstract translation: 在由第一半导体材料形成的衬底上沉积由第二半导体材料形成的第一覆盖层。 由第三半导体材料形成的第二覆盖层沉积在第一覆盖层上。 图案化第一和第二覆盖层以限定翅片，其中每个翅片包括在由第二材料形成的第二区域上由第三材料形成的第一区域。 氧化物填充翅片之间的空间。 然后进行热氧化以将第二区域转换为将由第三材料形成的第一区域与衬底绝缘的材料。 作为可选步骤，在沉积氧化物材料并进行热氧化之前，由第二材料形成的第二区域被水平地薄化。 一旦翅片形成并与衬底绝缘，就进行常规的FinFET制造。

公开(公告)号：US20150093861A1

公开(公告)日：2015-04-02

申请号：US14042884

申请日：2013-10-01

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare

IPC: H01L21/84

CPC classification number: H01L21/84

Abstract: An SOI substrate includes first and second active regions separated by STI structures and including gate stacks. A spacer layer conformally deposited over the first and second regions including the gate stacks is directionally etched to define sidewall spacers along the sides of the gate stacks. An oxide layer and nitride layer are then deposited. Using a mask, the nitride layer over the first active region is removed, and the mask and oxide layer are removed to expose the SOI substrate in the first active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the first active region and a protective nitride layer is deposited. The masking, nitride layer removal, and oxide layer removal steps are then repeated to expose the SOI in the second active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the second active region.

Abstract translation: SOI衬底包括由STI结构分离并且包括栅叠层的第一和第二有源区。 在包括栅极堆叠的第一和第二区域上共形沉积的间隔层被定向蚀刻以沿着栅极堆叠的侧面限定侧壁间隔物。 然后沉积氧化物层和氮化物层。 使用掩模，去除第一有源区上的氮化物层，去除掩模和氧化物层以暴露第一有源区中的SOI衬底。 然后在第一有源区中与栅叠层相邻地外延生长凸起的源极 - 漏极结构，并且沉积保护性氮化物层。 然后重复掩模，氮化物层去除和氧化物层去除步骤以暴露第二有源区域中的SOI。 然后在第二活性区域中与栅叠层相邻地外延生长凸起的源极 - 漏极结构。