公开(公告)号：US09425087B1

公开(公告)日：2016-08-23

申请号：US14725600

申请日：2015-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Chen ,  Che-Cheng Chang ,  Tai-Shin Cheng ,  Wei-Yin Shiao

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/76811 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate. The method includes forming a mask layer over the dielectric layer. The mask layer has an opening exposing a portion of the dielectric layer. The method includes removing the portion of the dielectric layer through the opening to form a recess in the dielectric layer. The method includes removing the mask layer. The method includes performing a plasma cleaning process over the dielectric layer. The plasma cleaning process uses a carbon dioxide-containing gas.

Abstract translation: 提供一种形成半导体器件结构的方法。 该方法包括在半导体衬底上形成电介质层。 该方法包括在电介质层上形成掩模层。 掩模层具有露出电介质层的一部分的开口。 该方法包括通过开口去除电介质层的部分，以在电介质层中形成凹陷。 该方法包括去除掩模层。 该方法包括在电介质层上执行等离子体清洗工艺。 等离子体清洁过程使用含二氧化碳的气体。

公开(公告)号：US09391205B2

公开(公告)日：2016-07-12

申请号：US14517272

申请日：2014-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Jr-Jung Lin

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/31144 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/32137 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a metal gate structure formed over a fin structure of the substrate. The semiconductor structure further includes a spacer formed on a sidewall of the metal gate structure and a source/drain structure formed in the fin structure. In addition, the spacer is in direct contact with the fin structure.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括在基板的翅片结构上形成的基板和金属栅极结构。 半导体结构还包括形成在金属栅极结构的侧壁上的隔离物和形成在鳍结构中的源极/漏极结构。 此外，间隔件与翅片结构直接接触。

公开(公告)号：US12237417B2

公开(公告)日：2025-02-25

申请号：US18061862

申请日：2022-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/82 ,  H01L21/3213 ,  H01L21/66 ,  H01L21/67 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  G01N21/88

Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

公开(公告)号：US12211750B2

公开(公告)日：2025-01-28

申请号：US17808709

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chang-Yin Chen ,  Jr-Jung Lin ,  Chih-Han Lin ,  Yung-Jung Chang

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

公开(公告)号：US11935889B2

公开(公告)日：2024-03-19

申请号：US17097423

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/08 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/66545

Abstract: A method includes, in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second device regions simultaneously. A first semiconductor strip is formed between the first recesses. A second semiconductor strip is formed between the second recesses. In a second etching step, the semiconductor substrate in the second device region is etched to extend the second recesses. The first recesses and the second recesses are filled with a dielectric material to form first and second isolation regions in the first and second recesses, respectively. The first isolation regions and the second isolation regions are recessed. Portions of the semiconductor substrate in the first and the second device regions protrude higher than top surfaces of the respective first and second isolation regions to form a first and a second semiconductor fin, respectively.

公开(公告)号：US20240030319A1

公开(公告)日：2024-01-25

申请号：US18473721

申请日：2023-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Po-Chi Wu ,  Che-Cheng Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/10

CPC classification number: H01L29/66818 ,  H01L29/7848 ,  H01L29/66795 ,  H01L21/3065 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/165

Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.

公开(公告)号：US11817503B2

公开(公告)日：2023-11-14

申请号：US17875152

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/42356 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A device includes a substrate, a shallow trench isolation (STI) structure, an isolation structure, and a gate stack. The substrate has a semiconductor fin. The shallow trench isolation (STI) structure is over the substrate and laterally surrounding the semiconductor fin. The isolation structure is disposed on a top surface of the STI structure. The gate stack crosses the semiconductor fin, over the STI structure, and in contact with a sidewall the isolation structure, in which the gate stack includes a high-k dielectric layer extending from a sidewall of the semiconductor fin to the top surface of the STI structure and terminating prior to reaching the sidewall of the isolation structure, and the high-k dielectric layer is in contact with the top surface of the STI structure. The gate stack includes a gate electrode over the high-k dielectric layer and in contact with the sidewall of the isolation structure.

公开(公告)号：US20230275142A1

公开(公告)日：2023-08-31

申请号：US18313190

申请日：2023-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Jui-Ping Chuang ,  Chen-Hsiang Lu ,  Yu-Cheng Liu ,  Wei-Ting Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L29/785 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/42372 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7848 ,  H01L29/7851 ,  H01L21/31111 ,  H01L21/76224

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

公开(公告)号：US20230116545A1

公开(公告)日：2023-04-13

申请号：US18065184

申请日：2022-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first metal layer formed over a substrate and a dielectric layer formed over the first metal layer. The semiconductor device structure further includes an adhesion layer formed in the dielectric layer and over the first metal layer and a second metal layer formed in the dielectric layer. The second metal layer is electrically connected to the first metal layer, and a portion of the adhesion layer is formed between the second metal layer and the dielectric layer. The adhesion layer includes a first portion lining with a top portion of the second metal layer, and the first portion has an extending portion along a vertical direction.

公开(公告)号：US20220270928A1

公开(公告)日：2022-08-25

申请号：US17739899

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/423

Abstract: A method includes providing a substrate having a channel region, forming a gate stack layer over the channel region, forming a patterned hard mask over the gate stack layer, etching a top portion of the gate stack layer through openings in the patterned hard mask with a first etchant, etching a middle portion and a bottom portion of the gate stack layer with a second etchant that includes a passivating gas. A gate stack is formed with a passivation layer deposited on sidewalls of the gate stack. The method also includes etching the gate stack with a third etchant, thereby removing a bottom portion of the passivation layer and recessing a bottom portion of the gate stack.