公开(公告)号：US20190252259A1

公开(公告)日：2019-08-15

申请号：US15893672

申请日：2018-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Chun-Hsien Lin ,  Wei-Hao Huang ,  Kai-Teng Cheng

IPC: H01L21/8234 ,  H01L21/30 ,  H01L21/28 ,  H01L21/321

CPC classification number: H01L21/82345 ,  H01L21/28088 ,  H01L21/3003 ,  H01L21/3212 ,  H01L21/823462

Abstract: The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.

公开(公告)号：US10312238B2

公开(公告)日：2019-06-04

申请号：US15803852

申请日：2017-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Yu-Ru Yang ,  Chih-Chien Liu ,  Chao-Ching Hsieh ,  Chun-Hsien Lin

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/02 ,  H01L27/22 ,  H01L27/105 ,  G11C11/16 ,  H01L23/528 ,  H01L43/10 ,  H01L43/08

Abstract: A manufacturing method of a magnetic random access memory (MRAM) cell includes the following steps. A magnetic tunnel junction (MTJ) film stack is formed on an insulation layer. An aluminum mask layer is formed on the MTJ film stack. A hard mask layer is formed on the aluminum mask layer. An ion beam etching (IBE) process is performed with the aluminum mask layer and the hard mask layer as a mask. The MTJ film stack is patterned to be a patterned MTJ film stack by the IBE process, and at least apart of the aluminum mask layer is bombarded by the IBE process for forming an aluminum film on a sidewall of the patterned MTJ film stack. An oxidation treatment is performed, and the aluminum film is oxidized to be an aluminum oxide protection layer on the sidewall of the patterned MTJ film stack by the oxidation treatment.

公开(公告)号：US20190157274A1

公开(公告)日：2019-05-23

申请号：US15841257

申请日：2017-12-13

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Chun-Hsien Lin ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L29/49

CPC classification number: H01L27/10823 ,  H01L21/0214 ,  H01L27/10876 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/4991 ,  H01L29/518

Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.

公开(公告)号：US20190139959A1

公开(公告)日：2019-05-09

申请号：US15803852

申请日：2017-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Yu-Ru Yang ,  Chih-Chien Liu ,  Chao-Ching Hsieh ,  Chun-Hsien Lin

IPC: H01L27/105 ,  G11C11/16 ,  H01L23/528 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A manufacturing method of a magnetic random access memory (MRAM) cell includes the following steps. A magnetic tunnel junction (MTJ) film stack is formed on an insulation layer. An aluminum mask layer is formed on the MTJ film stack. A hard mask layer is formed on the aluminum mask layer. An ion beam etching (IBE) process is performed with the aluminum mask layer and the hard mask layer as a mask. The MTJ film stack is patterned to be a patterned MTJ film stack by the IBE process, and at least apart of the aluminum mask layer is bombarded by the IBE process for forming an aluminum film on a sidewall of the patterned MTJ film stack. An oxidation treatment is performed, and the aluminum film is oxidized to be an aluminum oxide protection layer on the sidewall of the patterned MTJ film stack by the oxidation treatment.

公开(公告)号：US10283412B2

公开(公告)日：2019-05-07

申请号：US15697462

申请日：2017-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia Chang Hsu ,  Chun-Hsien Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/768 ,  H01L21/28 ,  H01L23/485 ,  H01L23/532

Abstract: A method for fabricating a semiconductor device is provided. A substrate having a dummy gate thereon is prepared. A spacer is disposed on a sidewall of the dummy gate. A source/drain region is disposed adjacent to the dummy gate. A sacrificial layer is then formed on the source/drain region. A cap layer is then formed on the sacrificial layer. A top surface of the cap layer is coplanar with a top surface of the dummy gate. A replacement metal gate (RMG) process is performed to transform the dummy gate into a replacement metal gate. An opening is then formed in the cap layer to expose a top surface of the sacrificial layer. The sacrificial layer is removed through the opening, thereby forming a lower contact hole exposing a top surface of the source/drain region. A lower contact plug is then formed in the lower contact hole.

公开(公告)号：US20190043979A1

公开(公告)日：2019-02-07

申请号：US15691779

申请日：2017-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L29/20

Abstract: A method for fabricating a tunnel field effect transistor (TFET) includes the steps of providing a substrate and then forming an interfacial layer on the substrate. Preferably, the step of forming the interfacial layer includes the steps of: performing a plasma treatment process to inject a first gas containing nitrogen; injecting a second gas containing oxygen; and injecting a precursor to react with the first gas and the second gas for forming the interfacial layer.

公开(公告)号：US10147795B1

公开(公告)日：2018-12-04

申请号：US15674526

申请日：2017-08-11

Applicant: United Microelectronics Corp.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L21/336 ,  H01L29/78 ,  H03K17/74 ,  H01L29/423 ,  H01L29/417 ,  H01L29/49 ,  H01L29/20 ,  H01L29/66

Abstract: A tunneling field effect transistor includes a semiconductor substrate, a source region, a tunneling region, a drain region, a gate electrode, and a gate dielectric layer. The source region is disposed on the semiconductor substrate, the tunneling region is disposed on the source region and includes a sidewall and a top surface, the drain region is disposed on the tunneling region, and the gate dielectric layer is disposed between the gate electrode and the tunneling region. The gate electrode is disposed on the source region and the tunneling region and includes a first gate electrode and a second electrode. The first gate electrode is disposed on the sidewall of the tunneling region, and the second gate electrode is disposed on the top surface of the tunneling region. The composition of the first gate electrode is different from the composition of the second gate electrode.

公开(公告)号：US10043868B2

公开(公告)日：2018-08-07

申请号：US15249462

申请日：2016-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Chun-Hsien Lin ,  Wen-An Liang

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure and method of forming the same. The semiconductor structure includes a fin structure formed on a substrate and an isolation structure formed therein. The isolation structure includes a trench with a concave upper sidewall, a straight lower sidewall and a rounded top corner. A first dielectric layer fills a lower portion of the trench. A second dielectric layer covers a top surface of the first dielectric layer, the concave upper sidewall and the rounded top corner of the trench.

公开(公告)号：US20180190785A1

公开(公告)日：2018-07-05

申请号：US15394833

申请日：2016-12-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4983 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7851

Abstract: A semiconductor device including a semiconductor substrate, agate on the semiconductor substrate, a drain doping region in the semiconductor substrate on a first side of the gate, a source doping region in the semiconductor substrate on a second side of the gate, a first spacer structure on a first sidewall of the gate between the gate and the drain doping region, and a second spacer structure on a second sidewall of the gate between the gate and the source doping region. The first spacer structure is composed of a low-k dielectric layer on the first sidewall of the gate and a first spacer material layer on the low-k dielectric layer. The second spacer structure is composed of a second spacer material layer on the second sidewall of the gate.

公开(公告)号：US20180166571A1

公开(公告)日：2018-06-14

申请号：US15861700

申请日：2018-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L23/532 ,  H01L29/267 ,  H01L29/24 ,  H01L29/165 ,  H01L29/16 ,  H01L29/161 ,  H01L29/08 ,  H01L21/768 ,  H01L29/66 ,  H01L23/535

CPC classification number: H01L29/7848 ,  H01L21/283 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76895 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7845

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first recess adjacent to two sides of the gate structure; forming an epitaxial layer in the first recess; removing part of the epitaxial layer to forma second recess; and forming an interlayer dielectric (ILD) layer on the gate structure and into the second recess.