公开(公告)号：US20210143104A1

公开(公告)日：2021-05-13

申请号：US16680978

申请日：2019-11-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Suming Hu ,  Roden Topacio ,  Farshad Ghahghahi ,  Jianguo Li ,  Andrew Kwan Wai Leung

IPC: H01L23/544 ,  H01L23/18 ,  H01L23/12

Abstract: An apparatus includes a substrate including an identification code on a first side of the substrate and near a perimeter of the substrate. The apparatus includes a stiffener structure attached to the first side of the substrate. The stiffener structure has a cutout in an outer perimeter of the stiffener structure. The stiffener structure is oriented with respect to the substrate to cause the cutout to expose the identification code. The cutout may have a first dimension and a second dimension orthogonal to the first dimension. The first dimension may exceed a corresponding first dimension of the identification code and the second dimension may exceed a corresponding second dimension of the identification code, thereby forming a void region between the identification code and edges of the stiffener structure.

公开(公告)号：US20210112289A1

公开(公告)日：2021-04-15

申请号：US17132304

申请日：2020-12-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Lei Zhang ,  Gabor Sines ,  Khaled Mammou ,  David Glen ,  Layla A. Mah ,  Rajabali M. Koduri ,  Bruce Montag

IPC: H04N21/2343 ,  H04L29/06 ,  H04N21/2368 ,  H04N21/434 ,  H04N21/414 ,  H04N21/422 ,  H04N21/43 ,  H04N21/437 ,  H04N21/236

Abstract: Virtual Reality (VR) processing devices and methods are provided for transmitting user feedback information comprising at least one of user position information and user orientation information, receiving encoded audio-video (A/V) data, which is generated based on the transmitted user feedback information, separating the A/V data into video data and audio data corresponding to a portion of a next frame of a sequence of frames of the video data to be displayed, decoding the portion of a next frame of the video data and the corresponding audio data, providing the audio data for aural presentation and controlling the portion of the next frame of the video data to be displayed in synchronization with the corresponding audio data.

公开(公告)号：US20210097184A1

公开(公告)日：2021-04-01

申请号：US16586226

申请日：2019-09-27

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Murali RAO ,  Clarence IP ,  Joseph SCANLON ,  Mihir S. DOCTOR ,  Norman STEWART ,  Guhan KRISHNAN

IPC: G06F21/57 ,  G06F21/51 ,  G06F9/4401 ,  G06F13/16

Abstract: A processing system isolates at a physically or logically separate memory region of a processing unit boot code that is received from an external boot source for programming a boot memory of the processing unit until after the boot code is validated to protect against buffer overruns that could compromise the processing system. The processing unit includes a secure buffer region of memory that is physically or logically isolated from the remainder of the processing unit for receiving boot code from an external boot source such as a personal computer (PC) such that any buffer overruns at the secure buffer simply overwrite data stored at the secure buffer, and do not affect data or instructions that are executing at the processing unit.

公开(公告)号：US20210092424A1

公开(公告)日：2021-03-25

申请号：US16579825

申请日：2019-09-23

Applicant: ATI Technologies ULC

Inventor： Guennadi Riguer ,  Ihab M. A. Amer

IPC: H04N19/46 ,  H04N19/513 ,  H04N19/156 ,  H04N19/146

Abstract: A technique for generating encoded video in a client-server system is provided. According to the technique, a server determines that reprojection analysis should occur. The server generates reprojection metadata based on suitability of video content to reprojection. The server generates encoded video based on the reprojection metadata, and transmits the encoded video to a client for display. The client reprojects video content as directed by the server.

公开(公告)号：US10957094B2

公开(公告)日：2021-03-23

申请号：US15250357

申请日：2016-08-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mikko Alho ,  Mika Tuomi ,  Kiia Kallio

IPC: G06T15/00 ,  G06T15/04

Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.

公开(公告)号：US10956338B2

公开(公告)日：2021-03-23

申请号：US16195435

申请日：2018-11-19

Applicant: ATI Technologies ULC

Inventor： Leon King Nok Lai ,  Qian Ma ,  Jimshed B. Mirza

IPC: G06F12/0891 ,  G06F3/06

Abstract: A technique for improving performance of a cache is provided. The technique involves maintaining indicators of whether cache entries are dirty in a random access memory (“RAM”) that has a lower latency to a cache controller than the cache memory that stores the cache entries. When a request to invalidate one or more cache entries is received by the cache controller, the cache controller checks the RAM to determine whether any cache entries are dirty and thus should be written out to a backing store. Using the RAM removes the need to check the actual cache memory for whether cache entries are dirty, which reduces the latency associated with performing such checks and thus with performing cache invalidations.

公开(公告)号：US20210056042A1

公开(公告)日：2021-02-25

申请号：US16548692

申请日：2019-08-22

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sonu ARORA ,  Paul BLINZER ,  Philip NG ,  Nippon Harshadk RAVAL

IPC: G06F12/1027 ,  G06F13/16

Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.

公开(公告)号：US10923430B2

公开(公告)日：2021-02-16

申请号：US16458094

申请日：2019-06-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Chun-Hung Lin ,  Rahul Agarwal ,  Milind Bhagavat ,  Fei Guo

IPC: H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer and an interconnect chip at least partially encased in the first molding layer. The interconnect chip has a first side and a second side opposite the first side and a polymer layer on the first side. The polymer layer includes plural conductor traces. A redistribution layer (RDL) structure is positioned on the first molding layer and has plural conductor structures electrically connected to the plural conductor traces. The plural conductor traces provide lateral routing.

公开(公告)号：US10915359B2

公开(公告)日：2021-02-09

申请号：US16195412

申请日：2018-11-19

Applicant: ATI Technologies ULC

Inventor： Jimshed B. Mirza ,  Qian Ma ,  Leon King Nok Lai

IPC: G06F9/50

Abstract: A technique for scheduling processing tasks having different latencies is provided. The technique involves identifying one or more available requests in a request queue, where each request queue corresponds to a different latency. A request arbiter examines a shift register to determine whether there is an available slot for the one or more requests. A slot is available for a request if there is a slot that is a number of slots from the end of the shift register equal to the number of cycles the request takes to complete processing in a corresponding processing pipeline. If a slot is available, the request is scheduled for execution and the slot is marked as being occupied. If a slot is not available, the request is not scheduled for execution on the current cycle. On transitioning to a new cycle, the shift register is shifted towards its end and the technique repeats.

公开(公告)号：US10909060B2

公开(公告)日：2021-02-02

申请号：US16216277

申请日：2018-12-11

Applicant: ATI Technologies ULC

Inventor： James Hunkins

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/38

Abstract: A data transmission medium includes first and second conductors and a first reversible plug connector coupled to a first end thereof. The first reversible plug connector includes a plurality of signal pins, a crossbar switch, a receiver, and a transmitter. In response to a first configuration state, the plurality of signal pins includes a first predetermined number of reception pins and a second predetermined number of transmission pins. The first and second predetermined numbers are different from each other and each is greater than zero. The crossbar switch couples the first predetermined number of reception pins to a first port and the second predetermined number of transmission pins to a second port. The receiver has an input coupled to the first conductor, and an output coupled to the first port. The transmitter has an input coupled to the second port and an output coupled to the second conductor.