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公开(公告)号：US10172105B2
公开(公告)日：2019-01-01
申请号：US15164363
申请日：2016-05-25
Applicant: Silicon Laboratories Inc.
Inventor： Hendricus de Ruijter , Ping Xiong , Wentao Li
Abstract: An apparatus includes a radio frequency (RF) receiver having a multi-bit observation interval. The RF receiver includes a Coordinate Rotation Digital Computer (Cordic) circuit to receive a complex signal derived from RF signals and to generate a phase signal. The RF receiver further includes a timing correlator and frequency offset estimator coupled to receive data derived from a frequency signal derived from the phase signal. The RF receiver in addition includes a Viterbi decoder coupled to provide decoded data derived from the frequency signal.
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公开(公告)号：US10165516B2
公开(公告)日：2018-12-25
申请号：US15196523
申请日：2016-06-29
Applicant: Silicon Laboratories Inc.
Inventor： Vitor M. Pereira
Abstract: Systems and methods are provided that may be implemented to selectively enable relatively higher data throughput and higher power WiFi bidirectional wireless protocol capability during times of system wireless activity, and to selectively disable the WiFi bidirectional wireless protocol and enable relatively lower data throughput and lower power wireless protocol capability during the absence of such system wireless activity. The systems and methods may be implemented to enable bi-directional wireless communication and/or external activation of a wireless device both during times of wireless device activity and during times in which wireless device activity is absent and/or a wireless device is inactive and not transmitting.
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公开(公告)号：US10141971B1
公开(公告)日：2018-11-27
申请号：US15815920
申请日：2017-11-17
Applicant: Silicon Laboratories Inc.
Inventor： Mohamed Elkholy , Ayman Shafik , Yang Gao , Arup Mukherji , Navin Harwalkar
Abstract: Embodiments of transceiver circuits disclosed herein include a first amplifier coupled to receive signals from an antenna during a receive (RX) mode of the transceiver circuit, a second amplifier coupled to transmit signals to the antenna during a transmit (TX) mode of the transceiver circuit, and a single impedance matching network coupled to the antenna and directly connected to a shared node to which the first and second amplifiers are directly connected. The single impedance matching network is configured to transform an impedance of the antenna into a resistance at the shared node. A control circuit is coupled to control the impedance transformation of the single impedance matching network, so as to provide a first resistance at the shared node during RX mode and a second resistance at the shared node during TX mode, wherein the second resistance is different from the first resistance.
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公开(公告)号：US10110177B1
公开(公告)日：2018-10-23
申请号：US15662375
申请日：2017-07-28
Applicant: Silicon Laboratories Inc.
Inventor： Mustafa Koroglu
Abstract: In one aspect, an apparatus includes: a first power amplifier to receive a first voltage signal and to output a first current; a second power amplifier to receive a second voltage signal and to output a second current; and a transformer coupled to the first power amplifier and the second power amplifier. The transformer may have multiple differential input ports to realize a controllable impedance based on a desired output power level.
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公开(公告)号：US10084376B2
公开(公告)日：2018-09-25
申请号：US13917387
申请日：2013-06-13
Applicant: Silicon Laboratories Inc.
Inventor： Sean A. Lofthouse
CPC classification number: H02M3/155 , H02M2001/0045 , H02M2001/009 , Y10T307/406
Abstract: A circuit such as a subscriber line interface circuit (SLIC) has a multiple output power converter including an inductive converter, a first passive rectifier, a first capacitor, and a second passive rectifier. The inductive converter has a voltage input terminal for receiving an input voltage, and a voltage output terminal. The first passive rectifier has an input coupled to the voltage output terminal of the inductive power converter, and an output for providing a first power supply voltage. The first capacitor has a first terminal coupled to the output terminal of the inductive converter, and a second terminal. The second passive rectifier has an input coupled to the second terminal of the first capacitor, and an output terminal for providing a second power supply voltage different from the first power supply voltage.
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Patent Agency Ranking
公开(公告)号：US10067478B1
公开(公告)日：2018-09-04
申请号：US15837472
申请日：2017-12-11
Applicant: Silicon Laboratories Inc.
Inventor： Raghunandan Kolar Ranganathan
IPC: G04F10/00 , H03K3/033 , H03K5/1534 , H03K5/159
Abstract: The resolution of a time to digital converter (TDC) is improved by using a gain stage at the input of the fine TDC. A delay line receives a pulse corresponding to the time information and recirculates the pulse in the delay line by coupling an output of the delay line to an input of the delay line. An integrating fine TDC receives a number of pulses from the delay line corresponding to the desired gain.
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公开(公告)号：US10057051B2
公开(公告)日：2018-08-21
申请号：US14983830
申请日：2015-12-30
Applicant: Silicon Laboratories Inc.
Inventor： Yunteng Huang
CPC classification number: H04L7/0332 , H03L7/0805 , H03L7/081 , H03L7/085 , H03L7/093 , H03L7/0991 , H03L7/0994 , H04J3/0661 , H04L7/002 , H04L27/2272
Abstract: A more cost effective wander jitter filter utilizes an excursion detector that receives a timing difference between a first signal and a second signal and supplies a first adjustment amount if a magnitude of the timing difference is above a predetermined threshold and otherwise supplies a second adjustment amount of zero. A summing circuit adjusts a magnitude of the timing difference by the first or second adjustment amount. A loop filter receives the summing circuit output and controls an oscillator. The excursion detector output (first adjustment value or zero according to the magnitude of the timing difference) is low pass filtered and the low pass filtered is reintroduced into the oscillator output or the feedback loop. The excursion detector output is accumulated and used to adjust a phase of the feedback signal from the oscillator.
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公开(公告)号：US10041981B2
公开(公告)日：2018-08-07
申请号：US14927959
申请日：2015-10-30
Applicant: Silicon Laboratories Inc.
Inventor： Xiaodong Wang
Abstract: A capacitor sense system includes a pad for coupling to an external capacitor. A current digital to analog converter (DAC) supplies current to charge the external capacitor. A reference capacitor is charged by a current source. A first comparator compares a voltage across the external capacitor sensed at the pad to a reference voltage and generates a first comparison. A second comparator compares a voltage across a reference capacitor to the reference voltage and generates a second comparison. The stored first and second comparisons are used to control the current DAC. First and second AC coupling capacitors are coupled respectively between the pad and the first comparator and between the reference capacitor and the second comparator. Sensing at the pad allows more accuracy and the AC coupling capacitors provide better matching and allow for different DC biases to be set for the external capacitor and the first comparator.
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公开(公告)号：US10033421B2
公开(公告)日：2018-07-24
申请号：US15168318
申请日：2016-05-31
Applicant: Silicon Laboratories Inc.
Inventor： Vitor Pereira , Mustafa Koroglu , Ruifeng Sun , Ramin Khoini-Poorfard , Abdulkerim Coban , Yu Su , Krishna Pentakota
Abstract: In one example, a semiconductor die includes multi-standard, multi-channel expandable television/satellite receiver that can be flexibly implemented in a number of different configurations to enable incorporation into a plurality of different systems. The semiconductor die may include multiple tuners to receive and tune a terrestrial radio frequency (RF) signal and a satellite RF signal. These tuners may include different frequency synthesizers including voltage controlled oscillators (VCOs) to generate VCO signals at different frequencies, mixers to downconvert the RF signals to baseband signals using the VCO signals. In an implementation, the semiconductor die may further include shared circuitry coupled to the tuners to digitize, process and demodulate the baseband signals.
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公开(公告)号：US10008981B2
公开(公告)日：2018-06-26
申请号：US15096612
申请日：2016-04-12
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Brian G. Drost , Hendricus de Ruijter
IPC: H03B5/08 , H03B5/12 , H03L1/00 , H03B5/36 , H03L1/02 , H03L7/02 , H03L7/087 , H03L7/095 , H03L7/22 , H03L7/23 , H03L7/183 , H03L7/197
CPC classification number: H03B5/1234 , H03B5/12 , H03B5/1265 , H03B5/36 , H03L1/00 , H03L1/026 , H03L7/02 , H03L7/087 , H03L7/095 , H03L7/183 , H03L7/1976 , H03L7/22 , H03L7/23
Abstract: An integrated clock generator includes a tunable LC oscillator, a tunable frequency synthesizer, and a processor. The tunable LC oscillator has an input for receiving an oscillator control signal, and an output for providing an oscillator clock signal. The tunable frequency synthesizer has a clock input coupled to the output of the tunable LC oscillator, a control input for receiving a synthesizer control signal, and an output for providing a clock output signal. The processor has an input for receiving a data input signal, a first output for providing the oscillator control signal, and a second output for providing the synthesizer control signal. The processor provides the oscillator control signal and the synthesizer control signal such that the tunable frequency synthesizer generates the output clock signal at a frequency indicated by the data input signal, and provides the synthesizer control signal further in response to a dynamic condition.
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