公开(公告)号：US20220359714A1

公开(公告)日：2022-11-10

申请号：US17736767

申请日：2022-05-04

Applicant: Exagan SAS ,  STMicroelectronics International N.V.

Inventor： Matthieu NONGAILLARD ,  Thomas OHEIX

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L25/07

Abstract: The disclosure concerns an electronic device comprising, stacked from a first surface to a second surface, a first stack and a second stack of two high electron mobility transistors, referred to as first and second transistor, the first and the second stack each comprising, from an insulating layer, interposed between the first and the second stack, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first and a second set of electrodes, the first and the second set of electrodes being each provided with a source electrode, with a drain electrode, and with a gate electrode which are arranged so that the first and the second transistor form a half-arm of a bridge.

公开(公告)号：US20220359435A1

公开(公告)日：2022-11-10

申请号：US17733589

申请日：2022-04-29

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V.

Inventor： Stephane MONFRAY ,  Siddhartha DHAR ,  Alain FLEURY

IPC: H01L23/66 ,  H01L23/373 ,  H01L23/42 ,  H01L21/48

Abstract: The present disclosure relates to an electronic circuit comprising a semiconductor substrate, radiofrequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars topped by metallic tracks, at least two connection elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level. The electronic circuit further comprises, between the two connection elements, a trench crossing completely the stack of insulating layers of one metallization level and further crossing partially the stack of insulating layers of the metallization level the closest to the substrate, and a heat dissipation device adapted for dissipating heat out of the trench.

公开(公告)号：US11475960B2

公开(公告)日：2022-10-18

申请号：US17306266

申请日：2021-05-03

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Fabio Enrico Carlo Disegni ,  Laura Capecchi ,  Marcella Carissimi ,  Vikas Rana ,  Cesare Torti

IPC: G11C13/00 ,  G11C16/10 ,  G11C7/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30 ,  G11C16/32

Abstract: An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.

公开(公告)号：US11463098B2

公开(公告)日：2022-10-04

申请号：US17342416

申请日：2021-06-08

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Ankur Bal ,  Sri Ram Gupta ,  Rupesh Singh

IPC: H03M1/10 ,  H03M1/38 ,  H03M1/46

Abstract: An integrated circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a bit step selector. During testing of the ADC, the bit step selector selects a number of bits to be tested for a next analog test voltage based on digital values that are within an integer delta value of most recent digital value for a most recent analog test voltage.

公开(公告)号：US11444580B2

公开(公告)日：2022-09-13

申请号：US16837783

申请日：2020-04-01

Applicant: STMicroelectronics International N.V.

Inventor： Riju Biswas

IPC: H03F3/45 ,  H03F1/26 ,  H03F3/68

Abstract: An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.

公开(公告)号：US11431342B2

公开(公告)日：2022-08-30

申请号：US17521210

申请日：2021-11-08

Applicant: STMicroelectronics International N.V.

Inventor： Gagan Midha ,  Kallol Chatterjee ,  Anand Kumar ,  Ankit Gupta

IPC: H03L7/089 ,  H03L7/099 ,  H03L7/093 ,  H03L7/197

Abstract: A PLL includes an input comparison circuit comparing a reference signal to a divided feedback signal to thereby control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed, and produces an oscillator control signal causing an oscillator to generate an output signal. Divider circuitry divides the output signal by a divisor to produce the divided feedback signal. Divisor generation circuitry changes the divisor over time so the output signal ramps from a start frequency to an end frequency. Modification circuitry stores a first oscillator control signal equal to the value of the oscillator control signal when the frequency of the output signal is the start ramp frequency. When the frequency of the output signal reaches the end ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.

公开(公告)号：US11429478B2

公开(公告)日：2022-08-30

申请号：US16867325

申请日：2020-05-05

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Jain

IPC: G06F11/10 ,  G06F11/30 ,  G06F11/07 ,  G06F11/32 ,  G06F11/16

Abstract: A circuit and methods of operation thereof are provided for robust protection against soft errors. The circuit includes a first set of storage elements coupled to and configured to sample a set of data inputs at a first set of times. The circuit includes a second set of storage elements coupled to and configured to sample the set of data inputs at a second set of times. A first parity generator generates a first parity check for the set of data inputs and a second parity generator generates a second parity check for output of the first set of storage elements. An error correction unit compares the first parity check and the second parity check to detect occurrences of error conditions in the circuit. The error correction unit may control output or operating characteristics of the circuit as a result of error conditions detected.

公开(公告)号：US20220269410A1

公开(公告)日：2022-08-25

申请号：US17742987

申请日：2022-05-12

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Giuseppe DESOLI ,  Anuj GROVER ,  Thomas BOESCH ,  Surinder Pal SINGH ,  Manuj AYODHYAWASI

IPC: G06F3/06 ,  G06N3/08

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

公开(公告)号：US11418204B2

公开(公告)日：2022-08-16

申请号：US17519122

申请日：2021-11-04

Applicant: STMicroelectronics International N.V.

Inventor： Ankit Gupta

IPC: H03L7/099 ,  H03L7/093 ,  H03L7/089

Abstract: A calibration scheme is used to control PLL bandwidth and contain its spread. In open loop, the VCO control voltage is swept over a range of values and VCO output frequency is measured at each control voltage level. The gain KVCO is determined for each measured output frequency and a corresponding current magnitude for the variable magnitude charge pump is calculated from a ratio of a constant to the gain KVCO and correlated in a look-up table to the measured output frequency. Once calibration is completed, the PLL loop is closed and a calculated current magnitude is fetched from the look-up table based on a desired output frequency for the PLL circuit. The variable magnitude charge pump circuit is then controlled to generate a charge pump current with a magnitude corresponding to the fetched charge pump current magnitude.

公开(公告)号：US20220244308A1

公开(公告)日：2022-08-04

申请号：US17164570

申请日：2021-02-01

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Shiv Kumar Vats ,  Tripti Gupta

IPC: G01R31/3177 ,  G06F1/04 ,  G01R31/317

Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.