公开(公告)号：US20080299695A1

公开(公告)日：2008-12-04

申请号：US12045853

申请日：2008-03-11

Applicant: Luc Ouellet ,  Patrick Wright

Inventor： Luc Ouellet ,  Patrick Wright

IPC: H01L21/00

CPC classification number: B81C1/00071 ,  B81B2201/06 ,  B81C2201/0191

Abstract: A method is disclosed for making a MEMS device wherein anhydrous HF exposed silicon nitride is used as a temporary adhesion layer allowing the transfer of a layer from a Carrier Wafer to a Device Wafer.

Abstract translation: 公开了一种用于制造MEMS器件的方法，其中使用无水HF暴露的氮化硅作为允许将层从载体晶片转移到器件晶片的临时粘合层。

公开(公告)号：US20080286945A1

公开(公告)日：2008-11-20

申请号：US12218149

申请日：2008-07-10

Applicant: Francois J. Henley ,  Nathan W. Cheung

Inventor： Francois J. Henley ,  Nathan W. Cheung

IPC: H01L21/00

CPC classification number: H01L21/187 ,  B81C1/0038 ,  B81C2201/0191 ,  B81C2201/0192 ,  H01L21/2007 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/304 ,  H01L21/7624 ,  H01L21/76254 ,  H01L21/7813 ,  Y10S117/915 ,  Y10S156/93 ,  Y10S438/974 ,  Y10S438/977 ,  Y10T156/11 ,  Y10T156/1158 ,  Y10T156/19 ,  Y10T428/21 ,  Y10T428/24893 ,  Y10T428/249956

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

公开(公告)号：US20080182386A1

公开(公告)日：2008-07-31

申请号：US12080114

申请日：2008-03-31

Applicant: Francois J. Henley ,  Nathan W. Cheung

Inventor： Francois J. Henley ,  Nathan W. Cheung

IPC: H01L21/30

CPC classification number: H01L21/187 ,  B81C1/0038 ,  B81C2201/0191 ,  B81C2201/0192 ,  H01L21/2007 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/304 ,  H01L21/7624 ,  H01L21/76254 ,  H01L21/7813 ,  Y10S117/915 ,  Y10S156/93 ,  Y10S438/974 ,  Y10S438/977 ,  Y10T156/11 ,  Y10T156/1158 ,  Y10T156/19 ,  Y10T428/21 ,  Y10T428/24893 ,  Y10T428/249956

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract translation: 一种用于从供体衬底（10）形成材料（12）的膜的技术。 该技术具有将能量粒子（22）通过供体衬底（10）的表面引入到表面下方的选定深度（20）的步骤，其中颗粒具有相对较高的浓度以限定施主衬底材料（12） 高于所选深度。 能量源被引导到供体基底的选定区域，以在所选择的深度（20）处引发基底（10）的受控切割作用，因此，所述切割动作提供了扩张切割前沿，从而将供体材料从剩余的 部分供体基质。

公开(公告)号：US07335972B2

公开(公告)日：2008-02-26

申请号：US10713374

申请日：2003-11-13

Applicant: Rajen Chanchani

Inventor： Rajen Chanchani

IPC: H01L23/58 ,  H01L23/48 ,  H01L23/64 ,  H01L23/52 ,  G01R31/28

CPC classification number: H01L21/6835 ,  B81C1/00238 ,  B81C3/002 ,  B81C2201/0191 ,  B81C2203/058 ,  H01L21/6836 ,  H01L21/76898 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.

Abstract translation: 芯片上的微系统包括正常厚度的底部晶片，并且一系列薄化的晶片可以堆叠在底部晶片上，胶合和电互连。 互连层包括柔性介电材料，互连结构，并且可以包括嵌入式无源器件。 堆叠晶圆技术提供了非均匀集成，超小型化，性能更高，性能稳定且性价比最高的微系统封装。 包括电子，传感器，光学和MEMS的高度集成的微系统封装可以在体积和封装上小型化至瓶盖尺寸或更小。

公开(公告)号：US07172911B2

公开(公告)日：2007-02-06

申请号：US10504714

申请日：2003-02-14

Applicant: Edvard Kälvesten ,  Thorbjörn Ebefors ,  Niklas Svedin ,  H{dot over (a)}kan Westin

Inventor： Edvard Kälvesten ,  Thorbjörn Ebefors ,  Niklas Svedin ,  H{dot over (a)}kan Westin

IPC: H01L21/00

CPC classification number: B81C1/0015 ,  B81B2201/042 ,  B81C1/00142 ,  B81C3/002 ,  B81C2201/019 ,  B81C2201/0191 ,  B81C2203/058

Abstract: A method of making a deflectable, free hanging micro structure having at least one hinge member, the method includes the steps of providing a first sacrificial wafer having a single crystalline material constituting material forming the micro structure. A second semiconductor wafer including necessary components for forming the structure in cooperation with the first wafer is provided. Finite areas of a structured bonding material is provided, on one or both of the wafers at selected locations, the finite areas defining points of connection for joining the wafers. The wafers are bonded using heat and optionally pressure. Sacrificial material is etched away from the sacrificial wafer, patterning the top wafer by lithography is performed to define the desired deflectable microstructures having hinges, and subsequently silicon etch to make the structures.

Abstract translation: 一种制造具有至少一个铰链构件的可偏转的自由悬挂微结构的方法，所述方法包括以下步骤：提供具有形成微结构的单晶材料构成材料的第一牺牲晶片。 提供了包括与第一晶片协作形成结构的必要部件的第二半导体晶片。 在选定位置的一个或两个晶片上提供结构化接合材料的有限区域，限定用于接合晶片的连接点。 使用热和任选的压力将晶片接合。 牺牲材料被蚀刻离开牺牲晶片，通过光刻来图案化顶部晶片以限定具有铰链的期望的可偏转微结构，并随后进行硅蚀刻以制造结构。

公开(公告)号：US20060076649A1

公开(公告)日：2006-04-13

申请号：US11287371

申请日：2005-11-28

Applicant: Fabrice Letertre ,  Bruno Ghyselen ,  Olivier Rayssac

Inventor： Fabrice Letertre ,  Bruno Ghyselen ,  Olivier Rayssac

IPC: H01L29/06 ,  H01L23/544 ,  H01L23/58

CPC classification number: H01L21/187 ,  B81C1/00365 ,  B81C2201/0191 ,  C30B25/183 ,  H01L21/0237 ,  H01L21/0243 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/76254

Abstract: A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. This assembly can receive thick epitaxial layers thereon with concern of causing cracking of such layers.

公开(公告)号：US20040251539A1

公开(公告)日：2004-12-16

申请号：US10801065

申请日：2004-03-15

Inventor： Sadeg M. Faris ,  Jaujeng Lin

IPC: H01L035/34

CPC classification number: B81C1/00071 ,  B81C2201/019 ,  B81C2201/0191

Abstract: A novel thermoelectric cooler array and method of making the same are disclosed. The thermoelectric cooler array is a multistage thermoelectric cooler which provides a cascaded configuration for providing heat transfer from a cold sink to a heat sink. The multistage configuration provides for much higher heat transfer range and further provides benefit of thermoelectric cooling integrated with active electronic or optoelectronic components. The method of manufacturing the thermoelectric cooling array provides for n-type and p-type thermoelectric material substrates to be selectively bonded and sliced to create the desired stages of the multistage thermoelectric cooler.

Abstract translation: 公开了一种新型的热电冷却器阵列及其制造方法。 热电冷却器阵列是多级热电冷却器，其提供级联配置，用于提供从冷水槽到散热器的热传递。 多级配置提供更高的传热范围，并进一步提供与主动电子或光电子部件集成的热电冷却的优势。 制造热电冷却阵列的方法提供n型和p型热电材料基板，以选择性地粘合和切片以产生多级热电冷却器的期望的阶段。

公开(公告)号：US20040245521A1

公开(公告)日：2004-12-09

申请号：US10800148

申请日：2004-03-12

Inventor： Sadeg M. Faris

IPC: H01L035/24

CPC classification number: B81C1/00071 ,  B81C1/0038 ,  B81C2201/019 ,  B81C2201/0191

Abstract: A novel method of manufactring a microchannel plate (nullMCPnull) is disclosed. The method comprises the steps of ion implantation of a substrate, the subsequent formation of channels paterned on the surface of the substrate and bonding of the subsequent substrate to a handle wafer. The layers are subsequently cleaved and the steps repeated until a MCP structure is achieved. The resulting MCP structure is cost-effective as compared to conventional manufacturing processes and the resulting MCP structure exhibits a funneling effect. The MCP structure may also be used for optical signal amplification for a biochip array.

Abstract translation: 公开了一种制造微通道板（“MCP”）的新颖方法。 该方法包括以下步骤：衬底的离子注入，随后形成在衬底的表面上引导的通道并将随后的衬底接合到处理晶片。 这些层随后被切割，并重复这些步骤，直到达到MCP结构。 所得到的MCP结构与传统的制造工艺相比具有成本效益，并且所得到的MCP结构表现出漏斗效应。 MCP结构也可用于生物芯片阵列的光信号放大。

公开(公告)号：US06821342B2

公开(公告)日：2004-11-23

申请号：US10278471

申请日：2002-10-23

Applicant: Michael F. Mattes ,  Ralph B. Danzl

Inventor： Michael F. Mattes ,  Ralph B. Danzl

IPC: C30B2502

CPC classification number: B81C1/00182 ,  B81B2203/0315 ,  B81C2201/0191

Abstract: A method for forming a suspended microstructure is provided. The method includes providing a monocrystalline target substrate and subjecting the surface of the monocrystalline target substrate to ion implantation to form a microstructure layer at the surface of the monocrystalline target substrate. An epitaxial material layer is formed overlying the microstructure layer. A handle substrate is provided and a patterned interposed material layer is provided between the epitaxial material layer and the handle substrate. The epitaxial material layer, the patterned interposed material layer and the handle substrate are affixed. The method further includes thermally treating the monocrystalline target substrate to effect separation between the microstructure layer and a remainder of the monocrystalline target substrate.

Abstract translation: 提供一种用于形成悬浮微结构的方法。 该方法包括提供单晶靶基板，并使单晶靶基板的表面进行离子注入，以在单晶靶基板的表面形成微结构层。 形成覆盖微结构层的外延材料层。 提供了一个手柄基板，并且在外延材料层和手柄基板之间提供了图案化的夹层材料层。 外延材料层，图案化夹层材料层和手柄基板被固定。 该方法还包括热处理单晶靶基材以实现微结构层与单晶靶基板的其余部分之间的分离。

公开(公告)号：US20040102021A1

公开(公告)日：2004-05-27

申请号：US10642315

申请日：2003-08-15

Inventor： William D. Sawyer ,  Jeffrey T. Borenstein

IPC: H01L021/76 ,  H01L021/30 ,  H01L021/46

CPC classification number: B81C1/00182 ,  B81C1/00579 ,  B81C3/001 ,  B81C2201/0191

Abstract: The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer. The method includes providing an SOI wafer that has (i) a handle layer, (ii) a dielectric layer, and (iii) a device layer, wherein a mesa etch has been made on the device layer of the SOI wafer, providing a substrate, wherein a pattern has been etched onto the substrate, bonding the SOI wafer and the substrate together, removing the handle layer of the SOI wafer, removing the dielectric layer of the SOI wafer, then performing a structural etch on the device layer of the SOI wafer to define the device.

Abstract translation: 本发明提供了使用绝缘体上硅（SOI）晶片生产微电子机械系统（MEMS）和相关器件的一般制造方法。 该方法包括提供SOI晶片，其具有（i）手柄层，（ii）电介质层和（iii）器件层，其中在SOI晶片的器件层上进行台面蚀刻，提供衬底 其中图案已被蚀刻到衬底上，将SOI晶片和衬底接合在一起，去除SOI晶片的手柄层，去除SOI晶片的电介质层，然后对SOI的器件层进行结构蚀刻 晶圆来定义设备。