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    Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate
    171.
    发明授权
    Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate 有权

    公开(公告)号：US12224264B2

    公开(公告)日：2025-02-11

    申请号：US18385167

    申请日：2023-10-30

    Applicant: Intel Corporation

    Inventor： Rahul Jain ,  Ji Yong Park ,  Kyu Oh Lee

    IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

    TRANSMIT POWER CONTROL FOR DMRS BUNDLING FOR COVERAGE ENHANCEMENT
    174.
    发明申请
    TRANSMIT POWER CONTROL FOR DMRS BUNDLING FOR COVERAGE ENHANCEMENT 有权

    公开(公告)号：US20250048272A1

    公开(公告)日：2025-02-06

    申请号：US18723066

    申请日：2023-02-07

    Applicant: INTEL CORPORATION

    Inventor： Gang Xiong ,  Gregory Ermolaev ,  Dong Han ,  Bishwarup Mondal ,  Sergey Sosnin

    IPC: H04W52/14 ,  H04L5/16 ,  H04W52/32 ,  H04W52/58

    Abstract: A user equipment (UE) may determine one or more nominal time-domain windows (TDWs) for demodulation reference signals (DMRS) bundling for physical uplink control channel (PUCCH) transmissions of a PUCCH repetition. A start of a new actual TDW for the DMRS bunding is determined in response to an event which causes power consistency and phase continuity not to be maintained across the PUCCH transmissions of the PUCCH repetition. The UE may maintain power consistency and phase continuity within the new actual TDW across two PUCCH transmissions of the PUCCH repetition. The event may comprise a use of different power control parameters for the two of the PUCCH transmissions of the PUCCH repetition within one of the nominal TDWs.

    SUPPORT OF AUTHORIZATION OF USER EQUIPMENT BASED SENSING IN A MOBILE SYSTEM
    175.
    发明申请
    SUPPORT OF AUTHORIZATION OF USER EQUIPMENT BASED SENSING IN A MOBILE SYSTEM 有权

    公开(公告)号：US20250048088A1

    公开(公告)日：2025-02-06

    申请号：US18924720

    申请日：2024-10-23

    Applicant: Intel Corporation

    Inventor： Abhijeet KOLEKAR

    IPC: H04W12/02 ,  H04W12/08

    Abstract: This disclosure describes systems, methods, and devices related to sensing authorization. A device may transmit a request for sensing services to a network, the request including one or more parameters related to sensing. The device may receive an authorization response from the network based on a UE's subscription status and privacy settings. The device may execute sensing functions locally on the UE upon receiving authorization from the network. The device may transmit sensing data to the network for exposure to authorized clients. The device may update a UE's privacy profile related to sensing data via a communication with a network function.

    TECHNIQUES TO BALANCE POWER AND PERFORMANCE FOR ACCESS TO A STORAGE DEVICE
    176.
    发明申请
    TECHNIQUES TO BALANCE POWER AND PERFORMANCE FOR ACCESS TO A STORAGE DEVICE 有权

    公开(公告)号：US20250045219A1

    公开(公告)日：2025-02-06

    申请号：US18923535

    申请日：2024-10-22

    Applicant: Intel Corporation

    Inventor： Raghavendra RAO ,  Venkata Mahesh GUNNAM ,  Eliad Adi KLEIN ,  David HINES

    IPC: G06F13/16 ,  G06F13/42

    Abstract: Examples include techniques associated with causing a change to a configuration to access a storage device based on determined bandwidth capabilities for read and write transactions to the storage device and based on a determined needed bandwidth to complete monitored read and write transactions to the storage device. The configuration to be based, at least in part, on coupling to the storage device via a storage interface over a serial bus and the configuration to include a link width for the serial bus, a link speed for the serial bus, or a power state to operate the storage device.

    TUNABLE EDGE-COUPLED INTERFACE FOR SILICON PHOTONIC INTEGRATED CIRCUITS (PICs) AND METHOD FOR MAKING SAME
    177.
    发明申请
    TUNABLE EDGE-COUPLED INTERFACE FOR SILICON PHOTONIC INTEGRATED CIRCUITS (PICs) AND METHOD FOR MAKING SAME 有权

    公开(公告)号：US20250044537A1

    公开(公告)日：2025-02-06

    申请号：US18362033

    申请日：2023-07-31

    Applicant: Intel Corporation

    Inventor： Chia-Pin Chiu ,  Kaveh Hosseini

    IPC: G02B6/43 ,  G02B6/42

    Abstract: A tunable edge-coupled interface for photonic integrated circuits (PICs). The architecture can be identified by (1) an edge interface for optical coupling that exhibits a gap between an oxide cladding layer and the silicon substrate of the PIC die, (2) a perforated beam region above the gap in the oxide layer, wherein waveguide beams in the beam region provide a respective optical path for waveguides of the PIC, (3) actuator beams flanking the waveguide beams, the actuator beams include a heating element and are operated to tune the edge interface by inducing deflection of the edge interface, and (4) an application-specific target pitch of waveguides on the edge interface.

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