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    Semiconductor memory device
    171.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07977968B2

    公开(公告)日：2011-07-12

    申请号：US12288882

    申请日：2008-10-24

    Applicant: Yong-Ki Kim ,  Kyung-Hoon Kim

    Inventor： Yong-Ki Kim ,  Kyung-Hoon Kim

    IPC: H03K17/16 ,  H03K19/003

    CPC classification number: G11C7/1048 ,  G11C11/4093

    Abstract: A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control signal and the plurality of code signals and outputting a plurality of selection signals based on decoded signals; and an ODT block for providing an output data pad with impedance of a termination resistor which is selected in response to the plurality of selection signals.

    Abstract translation: 一种半导体存储器件，包括：用于基于从外部源输入的代码控制信号输出多个代码信号的代码通道; 用于解码芯片选择信号的终端电阻器解码器，芯片终端（ODT）控制信号和多个代码信号，并且基于解码的信号输出多个选择信号; 以及ODT块，用于为输出数据焊盘提供响应于所述多个选择信号而选择的终端电阻器的阻抗。

    Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus
    172.
    发明授权
    Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus 有权
    用于在高度集成的半导体存储装置中恢复时钟数据的电路和方法

    公开(公告)号：US07965582B2

    公开(公告)日：2011-06-21

    申请号：US12157287

    申请日：2008-06-09

    Applicant: Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

    Inventor： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

    IPC: G11C8/18

    CPC classification number: H03H11/26

    Abstract: Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

    Abstract translation: 用于恢复高度集成的半导体存储装置中的时钟数据的电路和方法包括：多个信号接收单元，被配置为通过多个输入/输出焊盘接收信号，并根据接收的参考时钟传送信号，信号接收单元被分成 多个相位检测单元，被配置为检测从信号接收单元的组输出的信号的相位;多个相位检测控制单元，被配置为控制相位检测单元，使得相位检测单元顺序地检测相位检测单元的相位; 从信号接收单元的每个组输出的信号和被配置为输出从相位检测单元输出的信号的通知单元。

    BUILDING THAT USES COMPOSITE LIGHT-WEIGHT PANELS FOR STRUCTURE AND A CONSTRUCTION METHOD THEREFOR
    173.
    发明申请
    BUILDING THAT USES COMPOSITE LIGHT-WEIGHT PANELS FOR STRUCTURE AND A CONSTRUCTION METHOD THEREFOR 有权
    建筑物采用复合轻质结构板及其构造方法

    公开(公告)号：US20110036048A1

    公开(公告)日：2011-02-17

    申请号：US12937518

    申请日：2009-04-23

    Applicant: Byung Hwa Lee ,  Kyung Hoon Kim

    Inventor： Byung Hwa Lee ,  Kyung Hoon Kim

    IPC: E04C2/284 ,  E04C2/24 ,  E04B1/62 ,  E04B2/00 ,  E04B7/00

    CPC classification number: E04B1/08 ,  E04C2/384

    Abstract: The present invention relates to a building that uses composite light-weight panels for structure and a construction method therefor, more particularly, to a building constructed without pillars using composite light weight panels for structure and a construction method therefor, wherein the building comprises: a steel floor made out of sectional steel for example; walls which are formed by joining composite light-weight panels for structure having steel structure frames installed at corners to the steel floor by welding or joining means, neighboring steel structure frames being joined together by welding or joining means to form walls; roof frames which are constituted by a steel structure and have a truss structure to be positioned on the top of the walls and joined to the wall panels by welding or joining means; wall inner/outer coverings applied to the inner/outer peripherals of the walls; and roof coverings applied to the outer peripheral face of the roof frame.

    Abstract translation: 本发明涉及一种使用复合轻量面板的结构及其施工方法的建筑物，更具体地，涉及一种使用复合轻量面板进行结构的建筑物及其施工方法，其中建筑物包括： 例如用截面钢制成的钢地板; 通过将通过焊接或接合装置的钢结构框架安装在钢地板上的钢结构框架结合的复合轻量面板形成的壁，相邻的钢结构框架通过焊接或接合装置连接在一起以形成壁; 屋顶框架由钢结构构成，并具有定位在墙壁顶部的桁架结构，并通过焊接或接合方式与壁板接合; 墙壁内/外覆盖层施加到墙壁的内外周边; 以及施加到屋顶框架的外周面的屋顶覆盖物。

    Duty correction circuit
    175.
    发明授权
    Duty correction circuit 有权
    负责校正电路

    公开(公告)号：US07800423B2

    公开(公告)日：2010-09-21

    申请号：US12343753

    申请日：2008-12-24

    Applicant: Kyung-Hoon Kim ,  Bo-Kyeom Kim

    Inventor： Kyung-Hoon Kim ,  Bo-Kyeom Kim

    IPC: H03K3/017

    CPC classification number: H03K5/1565 ,  H03K2005/00065

    Abstract: A duty correction circuit includes a duty ratio sensor for controlling a duty ratio sensing speed by a sensing speed control signal and outputting a correction signal by sensing a duty ratio of a clock, and a duty ratio corrector for controlling the duty ratio of the clock in response to the correction signal.

    Abstract translation: 占空比校正电路包括占空比传感器，用于通过感测速度控制信号控制占空比感测速度，并通过感测时钟的占空比来输出校正信号;以及占空比校正器，用于控制时钟的占空比 响应于校正信号。

    Delayed locked loop circuit
    178.
    发明授权
    Delayed locked loop circuit 失效
    延迟锁定回路电路

    公开(公告)号：US07710171B2

    公开(公告)日：2010-05-04

    申请号：US12164199

    申请日：2008-06-30

    Applicant: Kyung-Hoon Kim ,  Bo-Kyeom Kim ,  Taek-Sang Song

    Inventor： Kyung-Hoon Kim ,  Bo-Kyeom Kim ,  Taek-Sang Song

    IPC: H03L7/06

    CPC classification number: H03L7/0814 ,  H03L7/07 ,  H03L7/087 ,  H03L7/091 ,  H03L7/093

    Abstract: A delay locked loop circuit for compensating for a phase skew of a memory device includes a first delay locking unit configured to delay an external clock of the memory device by a first amount of delay to output a first internal clock, a second locking unit configured to delay the external clock by a second amount of delay to output a second internal clock, the second amount of delay being greater than the first amount of delay, and a selecting unit configured to select one of the first internal clock and the second internal clock as an internal clock of the memory device.

    Abstract translation: 用于补偿存储器件的相位偏移的延迟锁定环路包括：第一延迟锁定单元，被配置为将存储器件的外部时钟延迟第一延迟量以输出第一内部时钟;第二锁定单元，被配置为 将外部时钟延迟第二延迟量以输出第二内部时钟，第二延迟量大于第一延迟量，以及选择单元，被配置为选择第一内部时钟和第二内部时钟中的一个作为 存储器件的内部时钟。

    WASHING MACHINE AND METHOD OF CONTROLLING A WASHING MACHINE
    179.
    发明申请
    WASHING MACHINE AND METHOD OF CONTROLLING A WASHING MACHINE 有权
    洗衣机和洗衣机的控制方法

    公开(公告)号：US20100037401A1

    公开(公告)日：2010-02-18

    申请号：US12466513

    申请日：2009-05-15

    Applicant: Sun Cheol BAE ,  Kyung Hoon Kim ,  Han Su Jung ,  Jae Hyeok Choi ,  Ja In Koo

    Inventor： Sun Cheol BAE ,  Kyung Hoon Kim ,  Han Su Jung ,  Jae Hyeok Choi ,  Ja In Koo

    IPC: D06F33/00

    CPC classification number: D06F37/203 ,  D06F35/005

    Abstract: A washing machine and a method of controlling the washing machine may be provided. The washing machine may include a drum in which laundry are provided and rotated. A laundry amount may be sensed. The drum may operate at a first speed so that a part of the laundry tumbles within the drum and another part of the laundry adheres to the drum or the drum operates at a second speed so that the laundry adheres to the drum according to the sensed laundry amount. Accordingly, at a time of a dehydration cycle, stability of the washing machine and a laundry balancing can be ensured.

    Abstract translation: 可以提供洗衣机和控制洗衣机的方法。 洗衣机可以包括其中设置和旋转衣物的滚筒。 可以感测到衣物量。 滚筒可以以第一速度操作，使得衣物的一部分在滚筒内滚动并且衣物的另一部分粘附到滚筒或滚筒以第二速度操作，使得衣物根据感测到的衣物粘附到滚筒 量。 因此，在脱水循环时，可以确保洗衣机的稳定性和衣物平衡。

    SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
    180.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 失效
    半导体存储器件及其工作方法

    公开(公告)号：US20090323444A1

    公开(公告)日：2009-12-31

    申请号：US12277609

    申请日：2008-11-25

    Applicant: Kyung-Hoon Kim ,  Sang-Sic Yoon ,  Bo-Kyeom Kim

    Inventor： Kyung-Hoon Kim ,  Sang-Sic Yoon ,  Bo-Kyeom Kim

    IPC: G11C7/22

    CPC classification number: G11C7/1051 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225

    Abstract: A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines.

    Abstract translation: 一种半导体存储器件，包括第一时钟传输路径，其被配置为响应于使能信号通过时钟传输线接收在CML电平摆动的源时钟，并将源时钟转换为在CMOS电平摆动的时钟。 该装置还包括第二时钟传输路径，其被配置为响应于使能信号在CMOS电平摆动的时钟中转换源时钟，并且经由时钟传输线输出转换的时钟，以及配置为输出数据的数据输出单元 响应于第一和第二时钟传输线的输出时钟。

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