公开(公告)号：US11340686B2

公开(公告)日：2022-05-24

申请号：US16947973

申请日：2020-08-26

Applicant: Rambus Inc.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G06F1/324 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G06F1/3234 ,  G06F1/3287 ,  G06F5/06 ,  G11C7/04 ,  H03L7/081

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

公开(公告)号：US20220158637A1

公开(公告)日：2022-05-19

申请号：US17526830

申请日：2021-11-15

Applicant: Rambus Inc.

Inventor： Alain Rousson ,  Hui Song ,  Ravi Shivnaraine ,  Christopher Holdenried ,  Hector Villacorta

IPC: H03K19/00 ,  H03K19/0185

Abstract: The embodiments herein describe technologies for back-gate biasing of clock trees using a reference generator. A circuit includes a set of clock buffers and a programmable voltage reference generator to apply a voltage to a back gate of a transistor of the set of clock buffers.

公开(公告)号：US20220156207A1

公开(公告)日：2022-05-19

申请号：US17534125

申请日：2021-11-23

Applicant: Rambus Inc.

Inventor： John Eric Linstadt

IPC: G06F13/16 ,  G06F12/06 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G06F12/02

Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

公开(公告)号：US11335430B2

公开(公告)日：2022-05-17

申请号：US16823908

申请日：2020-03-19

Applicant: Rambus Inc.

Inventor： Christopher Haywood

IPC: G11C29/44 ,  G11C29/18 ,  G11C29/12 ,  G11C7/22 ,  G11C29/00

Abstract: Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.

公开(公告)号：US20220148643A1

公开(公告)日：2022-05-12

申请号：US17532745

申请日：2021-11-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  John E. Linstadt ,  Thomas A. Giovannini ,  Scott C. Best ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/00 ,  H01L25/065 ,  H01L25/10 ,  G11C11/4096 ,  H01L25/18

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US20220140828A1

公开(公告)日：2022-05-05

申请号：US17527511

申请日：2021-11-16

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: H03K19/00 ,  G11C5/06 ,  G11C7/10 ,  H03K19/0175 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  G11C5/14

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

公开(公告)号：US11302367B2

公开(公告)日：2022-04-12

申请号：US16148984

申请日：2018-10-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/10

Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.

公开(公告)号：US20220078052A1

公开(公告)日：2022-03-10

申请号：US17482659

申请日：2021-09-23

Applicant: Rambus Inc.

Inventor： Ramin Farjad-Rad

IPC: H04L25/03

Abstract: An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.

公开(公告)号：US20220070032A1

公开(公告)日：2022-03-03

申请号：US17400945

申请日：2021-08-12

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC: H04L25/03 ,  H01J37/00 ,  H01L21/311 ,  H01L21/67 ,  H01L21/683 ,  H01L21/768 ,  H01L29/66

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

公开(公告)号：US11258641B2

公开(公告)日：2022-02-22

申请号：US17181883

申请日：2021-02-22

Applicant: Rambus Inc.

Inventor： Nanyan Wang ,  Vadim Moshinsky ,  Prashant Choudhary

IPC: H04L25/03 ,  H04L27/02

Abstract: Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process. The received signal is repeatedly sampled by an analog-to-digital converter (ADC). Certain samples containing interference that cannot be cancelled by a CTLE in the sampled series are filtered out (discarded). The remaining samples are used to generate, over a selected evaluation window, a histogram of the sampled values. This histogram is used to calculate a figure of merit for the current CTLE parameter settings. The figures of merit for various CTLE parameter settings are compared to find the set of CTLE parameter settings that optimize the figure of merit and by extension, optimize the CTLE circuitry's performance at equalizing the received signal.