公开(公告)号：US11995353B2

公开(公告)日：2024-05-28

申请号：US17747676

申请日：2022-05-18

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Jonathan S. Parry

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for storing parity during refresh operations are described. In some examples, refresh operations may be performed on a memory device when the memory device is idle. For example, a refresh operation may entail performing a logical operation on first data and a first set of parity bits and second data and a second set of parity bits. The logical operation may generate a third set of parity bits which may be used for data retention purposes. Moreover, during a read operation, the third set of parity bits may be used to recover corrupt or otherwise invalid data in the event of an error.

公开(公告)号：US11977778B2

公开(公告)日：2024-05-07

申请号：US17691014

申请日：2022-03-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Jonathan S. Parry ,  Lakshmi Kalpana Vakati

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679

Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.

公开(公告)号：US11942174B2

公开(公告)日：2024-03-26

申请号：US17574024

申请日：2022-01-12

Applicant: Micron Technology, Inc.

Inventor： Chun S. Yeung ,  Deping He ,  Jonathan S. Parry

IPC: G11C29/42 ,  G11C7/04 ,  G11C29/12 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C7/04 ,  G11C29/1201 ,  G11C29/4401 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: Methods, systems, and devices for topology-based retirement in a memory system are described. In some examples, a memory system or memory device may be configured to evaluate error conditions relative to a physical or electrical organization of a memory array, which may support inferring the presence or absence of defects in one or more structures of a memory device. For example, based on various evaluations of detected errors, a memory system or a memory device may be able to infer a presence of a short-circuit, an open circuit, a dielectric breakdown, or other defects of a memory array that may be related to wear or degradation over time, and retire a portion of a memory array based on such an inference.

公开(公告)号：US20240071522A1

公开(公告)日：2024-02-29

申请号：US17895886

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Nicola Ciocchini ,  Animesh R. Chowdhury ,  Kishore Kumar Muchherla ,  Akira Goda ,  Jung Sheng Hoei ,  Niccolo' Righetti ,  Jonathan S. Parry

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/3427 ,  G11C16/08 ,  G11C16/26

Abstract: Methods, systems, and apparatuses include receiving a read command including a logical address. The read command is directed to a portion of memory composed of blocks and each block is composed of wordline groups. The physical address for the read command is identified using the logical address. The wordline group is determined using the physical address. A slope factor is retrieved using the wordline group. A read counter is incremented using the slope factor.

公开(公告)号：US20240070084A1

公开(公告)日：2024-02-29

申请号：US17898779

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Jonathan S. Parry ,  Akira Goda

IPC: G06F12/0891 ,  G06F12/0831 ,  G06F13/16

CPC classification number: G06F12/0891 ,  G06F12/0833 ,  G06F13/1668

Abstract: A victim management unit (MU) for performing a media management operation is identified. The victim MU stores valid data. A flush command is received from a host system. A cached data item is retrieved from a volatile memory. The cached data item and at least a subset of the valid data stored at the victim MU are written to a target MU.

公开(公告)号：US20240069765A1

公开(公告)日：2024-02-29

申请号：US17894794

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Robert Loren O. Ursua ,  Sead Zildzic ,  Eric N. Lee ,  Jonathan S. Parry ,  Lakshmi Kalpana K. Vakati ,  Jeffrey S. McNeil

IPC: G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/0625 ,  G06F3/0679

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

公开(公告)号：US20240069735A1

公开(公告)日：2024-02-29

申请号：US17898333

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chun Sum Yeung ,  Deping He ,  Ting Luo ,  Guang Hu ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0679

Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a metric associated with the memory array. Responsive to determine that the value of the metric is below a predetermined threshold, the processing device is further to initiate an erase protocol of the memory device. The processing device is further to erase sets of memory cells associated with one or more memory blocks of the memory array. The processing device is further to receive a programming command directed to the first set of memory cells. The processing device is further to perform a programming operation with respect to a set of memory cells responsive to receiving the programming command.

公开(公告)号：US20240061593A1

公开(公告)日：2024-02-22

申请号：US18234522

申请日：2023-08-16

Applicant: Micron Technology, Inc.

Inventor： Hojung Yun ,  Liang Yu ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0679

Abstract: A memory device includes memory dies. Each memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations for implementing peak power management (PPM) data burst communication. The operations include monitoring a data burst with respect to the memory array, detecting a current reservation trigger associated with the data burst, in response detecting the current reservation trigger, reserving an initial amount of current reflecting a maximum current consumption value associated with a maximum data transfer speed of the data burst, detecting a plurality of input/output cycles of the data burst following the preamble period, and in response to detecting the number of input/output cycles, reserving, based on an analysis of the plurality of input/output cycles, a subsequent amount of current reflecting an actual current consumption value associated with an actual data transfer speed of the data burst.

公开(公告)号：US20240061589A1

公开(公告)日：2024-02-22

申请号：US17890082

申请日：2022-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Jonathan S. Parry ,  Sivagnanam Parthasarathy ,  Akira Goda

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0629

Abstract: A method includes determining a logical saturation of a memory device in a memory sub-system and adjusting a code rate of the memory device based on the logical saturation, wherein the code rate represents a ratio of user data to a combination of the user data and error correction data.

公开(公告)号：US20240048788A1

公开(公告)日：2024-02-08

申请号：US18223932

申请日：2023-07-19

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Jonathan S. Parry

IPC: H04N21/2668 ,  H04N21/258 ,  H04N21/234 ,  H04N21/25 ,  H04N21/845

CPC classification number: H04N21/2668 ,  H04N21/25891 ,  H04N21/23418 ,  H04N21/251 ,  H04N21/8456

Abstract: Processing logic receives an indication of at least one of content preferences or contextual information associated with a request to view a media content stream and controls one or more parameters of the media content stream according to the at least one of the content preferences or contextual information to create a personalized media content stream. The processing logic further provides the personalized media content stream to a user device.