公开(公告)号：US10431281B1

公开(公告)日：2019-10-01

申请号：US16104711

申请日：2018-08-17

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Daniele Vimercati ,  Jahanshir Javanifard

IPC: G11C11/22

Abstract: Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.

公开(公告)号：US10388361B1

公开(公告)日：2019-08-20

申请号：US15920171

申请日：2018-03-13

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Stefan Frederik Schippers ,  Xinwei Guo

IPC: G11C11/24 ,  G11C11/4091 ,  G11C11/408 ,  H03F3/45 ,  G11C11/22

Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.

公开(公告)号：US10290341B2

公开(公告)日：2019-05-14

申请号：US15442182

申请日：2017-02-24

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22 ,  G11C27/02

Abstract: Methods, systems, and apparatuses for self-referencing memory cells are described. A reference value for a cell may be created through multiple sense operations on the cell. The cell may be sensed several times and an average of at least two sensing operations may be used as a reference for another sense operation. For example, the cell may be sensed and the resulting charge stored at a capacitor. The cell may be biased to one state, sensed a second time, and the resulting charge stored at another capacitor. The cell may be biased to another state, sensed a third time, and the resulting charge stored to another capacitor. The values from the second and third sensing operations may be averaged and used as a reference value in a comparison with value of the first sensing operation to determine a logic state of the cell.

公开(公告)号：US20190122717A1

公开(公告)日：2019-04-25

申请号：US16184276

申请日：2018-11-08

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

Abstract: Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.

公开(公告)号：US20180374527A1

公开(公告)日：2018-12-27

申请号：US16105790

申请日：2018-08-20

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Xinwei Guo

IPC: G11C11/22 ,  G11C29/00

Abstract: Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another memory cell is discovered to be defective in some way; for example, after the array is fabricated and before deployment, defects in portions of the array that affect certain memory cells may be identified. Memory cells may be designated as redundant cells for numerous other memory cells of the array so that a total number of redundant cells in the array is relatively small fraction of the total number of cells of the array. A configuration of switching components may allow redundant cells to be operated in a manner that supports redundancy for numerous other cells and may limit or disturbances to neighboring cells when accessing redundancy cells.

公开(公告)号：US20180190337A1

公开(公告)日：2018-07-05

申请号：US15855326

申请日：2017-12-27

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Scott James Derner ,  Umberto Di Vincenzo ,  Christopher John Kawamura ,  Eric S. Carman

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.

公开(公告)号：US20180068705A1

公开(公告)日：2018-03-08

申请号：US15689940

申请日：2017-08-29

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Xinwei Guo

IPC: G11C11/22

CPC classification number: G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C29/781 ,  G11C29/804 ,  G11C29/806 ,  G11C29/816

Abstract: Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another memory cell is discovered to be defective in some way; for example, after the array is fabricated and before deployment, defects in portions of the array that affect certain memory cells may be identified. Memory cells may be designated as redundant cells for numerous other memory cells of the array so that a total number of redundant cells in the array is relatively small fraction of the total number of cells of the array. A configuration of switching components may allow redundant cells to be operated in a manner that supports redundancy for numerous other cells and may limit or disturbances to neighboring cells when accessing redundancy cells.

公开(公告)号：US09779796B1

公开(公告)日：2017-10-03

申请号：US15258852

申请日：2016-09-07

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Xinwei Guo

IPC: G11C11/22

CPC classification number: G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C29/781 ,  G11C29/804 ,  G11C29/806 ,  G11C29/816

Abstract: Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another memory cell is discovered to be defective in some way; for example, after the array is fabricated and before deployment, defects in portions of the array that affect certain memory cells may be identified. Memory cells may be designated as redundant cells for numerous other memory cells of the array so that a total number of redundant cells in the array is relatively small fraction of the total number of cells of the array. A configuration of switching components may allow redundant cells to be operated in a manner that supports redundancy for numerous other cells and may limit or disturbances to neighboring cells when accessing redundancy cells.

公开(公告)号：US09767857B2

公开(公告)日：2017-09-19

申请号：US14668812

申请日：2015-03-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gerald John Barkley ,  Daniele Vimercati ,  Pierguido Garofalo

IPC: G11C5/02 ,  G11C8/12 ,  G11C16/08 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G11C13/00

CPC classification number: G11C5/025 ,  G11C7/1042 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.

公开(公告)号：US20170263304A1

公开(公告)日：2017-09-14

申请号：US15067954

申请日：2016-03-11

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be selected using a selection component that is in electronic communication with a sense amplifier and a ferroelectric capacitor of a ferroelectric memory cell. A voltage applied to the ferroelectric capacitor may be sized to increase the signal sensed during a read operation. The ferroelectric capacitor may be isolated from the sense amplifier during the read operation. This isolation may avoid stressing the ferroelectric capacitor which may otherwise occur due to the applied read voltage and voltage introduce by the sense amplifier during the read operation.