公开(公告)号：US09219158B2

公开(公告)日：2015-12-22

申请号：US14677262

申请日：2015-04-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu Miyairi ,  Takeshi Osada ,  Kengo Akimoto ,  Shunpei Yamazaki

IPC: H01L29/00 ,  H01L29/786 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L29/78648 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/42384 ,  H01L29/78645 ,  H01L29/7869 ,  H01L29/78696

Abstract: As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, there occurs a problem that it is difficult to mount an IC chip including a driver circuit for driving the gate and signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. The pixel portion and the driver portion are provided over the same substrate, whereby manufacturing cost can be reduced.

公开(公告)号：US09166058B2

公开(公告)日：2015-10-20

申请号：US14529529

申请日：2014-10-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu Miyairi ,  Kengo Akimoto ,  Yasuo Nakamura

IPC: H01L21/00 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/465 ,  H01L21/467 ,  H01L21/4763

CPC classification number: H01L29/78696 ,  H01L21/02323 ,  H01L21/02565 ,  H01L21/32139 ,  H01L21/465 ,  H01L21/467 ,  H01L21/4763 ,  H01L21/47635 ,  H01L27/1225 ,  H01L29/0692 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/263 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78693

Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

Abstract translation: 为了提供一种以少数步骤制造包括具有优异电特性和高可靠性的薄膜晶体管的半导体器件的方法。 在包含In，Ga和Zn的氧化物半导体膜上形成沟道保护层之后，形成具有n型导电性的膜和导电膜，并且在导电膜上形成抗蚀剂掩模。 使用沟道保护层和栅极绝缘膜作为具有抗蚀剂掩模的蚀刻阻挡层来蚀刻导电膜，具有n型导电性的膜和包含In，Ga和Zn的氧化物半导体膜，使得源极和漏极层 ，缓冲层和半导体层。

公开(公告)号：US09083334B2

公开(公告)日：2015-07-14

申请号：US13761302

申请日：2013-02-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun Koyama ,  Kengo Akimoto ,  Masashi Tsubuku

IPC: H03K19/20 ,  H03K19/094 ,  H01L27/12 ,  H03K19/096 ,  H01L27/088

CPC classification number: H03K19/094 ,  H01L27/0883 ,  H01L27/1225 ,  H03K19/09407 ,  H03K19/09421 ,  H03K19/096

Abstract: An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.

Abstract translation: 目的是将使用氧化物半导体的晶体管施加到包括增强晶体管的逻辑电路。 逻辑电路包括耗尽晶体管101和增强晶体管102.晶体管101和102各自包括栅电极，栅极绝缘层，第一氧化物半导体层，第二氧化物半导体层，源电极和漏电极 。 晶体管102包括在源电极和漏极之间的第一氧化物半导体层中的区域上设置的还原防止层。

公开(公告)号：US09064899B2

公开(公告)日：2015-06-23

申请号：US14204620

申请日：2014-03-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi Godo ,  Kengo Akimoto ,  Shunpei Yamazaki

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/78693 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02573 ,  H01L21/02631 ,  H01L29/24 ,  H01L29/66742 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced.

Abstract translation: 目的是为了减小阈值电压的变化，以稳定每个使用氧化物半导体层的薄膜晶体管的电特性。 目的是减少关断电流。 使用氧化物半导体层的薄膜晶体管通过在氧化物半导体层上层叠含有绝缘氧化物的氧化物半导体层而形成，使得氧化物半导体层和源极和漏极电极层彼此接触，氧化物半导体层包含绝缘体 介于其间的氧化物; 从而可以减小薄膜晶体管的阈值电压的变化，从而能够稳定电特性。 此外，可以减少截止电流。

公开(公告)号：US09034675B2

公开(公告)日：2015-05-19

申请号：US14299045

申请日：2014-06-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kengo Akimoto ,  Junichiro Sakata ,  Yoshiharu Hirakata ,  Norihito Sone

IPC: H01L27/32 ,  H01L51/56 ,  H01L51/50 ,  H01L51/52

CPC classification number: H01L27/3244 ,  H01L27/322 ,  H01L27/3276 ,  H01L51/5048 ,  H01L51/5088 ,  H01L51/5092 ,  H01L51/52 ,  H01L51/5206 ,  H01L51/5215 ,  H01L51/5218 ,  H01L51/5234 ,  H01L51/5237 ,  H01L51/5246 ,  H01L51/5253 ,  H01L51/5259 ,  H01L51/56

Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.

Abstract translation: 提供了用于制造具有高内部量子效率，消耗较少功率，具有高亮度并且具有高可靠性的发光装置的技术。 这些技术包括形成包含导电透光氧化物材料和氧化硅的导电透光氧化物层，形成阻挡层，其中氧化硅的密度高于导电光上的导电透光氧化物层的密度 形成具有导电透光性氧化物层和阻挡层的阳极，在真空气氛下加热阳极，在加热阳极上形成电致发光层，在电致发光层上形成阴极。 根据该技术，在电致发光层和导电透光性氧化物层之间形成阻挡层。

公开(公告)号：US20150093853A1

公开(公告)日：2015-04-02

申请号：US14489522

申请日：2014-09-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Suzunosuke Hiraishi ,  Kengo Akimoto ,  Junichiro Sakata

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/7869

Abstract: An object is, in a thin film transistor including an oxide semiconductor layer, to reduce contact resistance between the oxide semiconductor layer and source and drain electrode layers electrically connected to the oxide semiconductor layer. The source and drain electrode layers have a stacked-layer structure of two or more layers in which a layer in contact with the oxide semiconductor layer is formed using a metal whose work function is lower than the work function of the oxide semiconductor layer or an alloy containing such a metal. Layers other than the layer in contact with the oxide semiconductor layer of the source and drain electrode layers are formed using an element selected from Al, Cr, Cu, Ta, Ti, Mo, or W, an alloy containing any of these elements as a component, an alloy containing any of these elements in combination, or the like.

Abstract translation: 在包括氧化物半导体层的薄膜晶体管中，目的是减少氧化物半导体层与与氧化物半导体层电连接的源电极层和漏电极层之间的接触电阻。 源极和漏极电极层具有两层或多层的层叠结构，其中使用功函数低于氧化物半导体层的功函数或合金的金属形成与氧化物半导体层接触的层 含有这样的金属。 使用选自Al，Cr，Cu，Ta，Ti，Mo或W的元素形成与源极和漏极电极层的氧化物半导体层接触的层以外的层，包含任何这些元素作为 组分，包含任何这些元素组合的合金等。

公开(公告)号：US08994021B2

公开(公告)日：2015-03-31

申请号：US14199257

申请日：2014-03-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masashi Tsubuku ,  Kengo Akimoto ,  Hiroki Ohara ,  Tatsuya Honda ,  Takatsugu Omata ,  Yusuke Nonaka ,  Masahiro Takahashi ,  Akiharu Miyanaga

IPC: H01L29/12 ,  H01L29/04 ,  H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/247 ,  H01L29/7869 ,  H01L29/78693

Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm−1 and less than or equal to 0.7 nm−1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm−1 and less than or equal to 4.1 nm−1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm−1 and less than or equal to 1.4 nm−1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm−1 and less than or equal to 7.1 nm−1.

Abstract translation: 提供了具有更稳定的导电性的氧化物半导体膜。 氧化物半导体膜包含结晶区域。 氧化物半导体膜具有在散射矢量的大小为散射矢量的大小的区域中具有大于或等于0.4nm -1且小于或等于0.7nm -1的半高全宽的电子衍射强度的第一峰值 大于或等于3.3nm -1且小于或等于4.1nm -1。 氧化物半导体膜具有第二峰电子衍射强度，半导体全宽度大于或等于0.45nm-1且小于或等于1.4nm-1，其中散射矢量的大小为 大于或等于5.5nm -1且小于或等于7.1nm -1。

公开(公告)号：US08803146B2

公开(公告)日：2014-08-12

申请号：US13763874

申请日：2013-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kengo Akimoto ,  Daisuke Kawae

IPC: H01L29/04 ,  H01L29/10 ,  H01L31/00 ,  H01L21/00

CPC classification number: H01L29/41733 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0508 ,  H01L51/0512 ,  H01L51/0545 ,  H01L51/105

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Abstract translation: 下栅极薄膜晶体管中的源电极和漏电极之间可能发生的电场浓度被放宽并且抑制了开关特性的劣化的结构及其制造方法。 制造在源电极和漏电极上设置氧化物半导体层的底栅薄膜晶体管，与氧化物半导体层接触的源电极的侧表面的角度和角度;角度和角度; 与氧化物半导体层接触的漏电极的侧面的两个面积分别被设定为大于或等于20°且小于90°，​​使得从上边缘到下边缘的距离 每个电极的侧表面增加。

公开(公告)号：US08729547B2

公开(公告)日：2014-05-20

申请号：US13727056

申请日：2012-12-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu Miyairi ,  Kengo Akimoto ,  Yasuo Nakamura

IPC: H01L29/10

CPC classification number: H01L29/78696 ,  H01L21/02323 ,  H01L21/02565 ,  H01L21/32139 ,  H01L21/465 ,  H01L21/467 ,  H01L21/4763 ,  H01L21/47635 ,  H01L27/1225 ,  H01L29/0692 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/263 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78693

Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

Abstract translation: 为了提供一种以少数步骤制造包括具有优异电特性和高可靠性的薄膜晶体管的半导体器件的方法。 在包含In，Ga和Zn的氧化物半导体膜上形成沟道保护层之后，形成具有n型导电性的膜和导电膜，并且在导电膜上形成抗蚀剂掩模。 使用沟道保护层和栅极绝缘膜作为具有抗蚀剂掩模的蚀刻阻挡层来蚀刻导电膜，具有n型导电性的膜和包含In，Ga和Zn的氧化物半导体膜，使得源极和漏极层 ，缓冲层和半导体层。

公开(公告)号：US08643011B2

公开(公告)日：2014-02-04

申请号：US13677504

申请日：2012-11-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kengo Akimoto ,  Junichiro Sakata ,  Takuya Hirohashi ,  Masahiro Takahashi ,  Hideyuki Kishida ,  Akiharu Miyanaga

IPC: H01L29/15

CPC classification number: H01L29/7869 ,  H01L21/02565 ,  H01L21/28079 ,  H01L21/28158 ,  H01L29/04 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78693

Abstract: It is an object to provide an oxide semiconductor which is suitable for use in a semiconductor device. Alternatively, it is another object to provide a semiconductor device using the oxide semiconductor. Provided is a semiconductor device including an In—Ga—Zn—O based oxide semiconductor layer in a channel formation region of a transistor. In the semiconductor device, the In—Ga—Zn—O based oxide semiconductor layer has a structure in which crystal grains represented by InGaO3(ZnO)m (m=1) are included in an amorphous structure represented by InGaO3(ZnO)m (m>0).

Abstract translation: 本发明的目的是提供一种适用于半导体器件的氧化物半导体。 或者，另一目的是提供一种使用氧化物半导体的半导体器件。 提供了在晶体管的沟道形成区域中包括In-Ga-Zn-O系氧化物半导体层的半导体器件。 在半导体器件中，In-Ga-Zn-O系氧化物半导体层具有以InGaO 3（ZnO）m（m = 1）表示的晶粒包含在由InGaO 3（ZnO）m（ m> 0）。