公开(公告)号：US09922974B2

公开(公告)日：2018-03-20

申请号：US15641336

申请日：2017-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia Chang Hsu ,  Chun-Hsien Lin

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/40 ,  H01L21/8234 ,  H01L23/485

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/76819 ,  H01L21/76853 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/401 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.

公开(公告)号：US20170077257A1

公开(公告)日：2017-03-16

申请号：US14880275

申请日：2015-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L29/42376

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, and an interlayer dielectric disposed on the substrate which has agate structure therein. The gate structure further includes a gate electrode with a protruding portion, and a gate dielectric layer disposed between the gate electrode and the substrate. A spacer is disposed between the interlayer dielectric and the gate electrode. An insulating cap layer is disposed atop the gate electrode and encompasses the top and the sidewall of the protruding portion.

Abstract translation: 公开了半导体结构。 半导体结构包括衬底和设置在其上具有玛瑙结构的衬底上的层间电介质。 栅极结构还包括具有突出部分的栅极电极和设置在栅极电极和衬底之间的栅极电介质层。 间隔物设置在层间电介质和栅电极之间。 绝缘盖层设置在栅极顶部并且包围突出部分的顶部和侧壁。

公开(公告)号：US09455227B1

公开(公告)日：2016-09-27

申请号：US14935456

申请日：2015-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Chih-Sen Huang ,  Chun-Hsien Lin

IPC: H01L29/94 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/28123 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0653 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成第一栅极结构; 形成与所述第一栅极结构相邻的第一接触插塞; 并执行替换金属栅极（RMG）处理，以将第一栅极结构转换成金属栅极。

公开(公告)号：US09196546B2

公开(公告)日：2015-11-24

申请号：US14025833

申请日：2013-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/76 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A metal gate transistor is disclosed. The metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate. The metal gate further includes a high-k dielectric layer, a bottom barrier metal (BBM) layer on the high-k dielectric layer, a first work function layer on the BBM layer, a second work function layer between the BBM layer and the first work function layer, and a low resistance metal layer on the first work function layer. Preferably, the first work function layer includes a p-type work function layer and the second work function layer includes a n-type work function layer.

Abstract translation: 公开了一种金属栅极晶体管。 金属栅极晶体管包括衬底，衬底上的金属栅极和衬底中的源极/漏极区域。 金属栅极还包括高k电介质层，高k电介质层上的底部阻挡金属（BBM）层，BBM层上的第一功函数层，BBM层和第一层之间的第二功函数层 功函数层，第一功函数层上的低电阻金属层。 优选地，第一功函数层包括p型功函数层，第二功函数层包括n型功函数层。

公开(公告)号：US20150295090A1

公开(公告)日：2015-10-15

申请号：US14749648

申请日：2015-06-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Rai-Min Huang ,  Sheng-Huei Dai ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/7853 ,  H01L21/02647 ,  H01L21/2022 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785 ,  H01L2029/7858

Abstract: A Fin-FET and a method of forming the Fin-FET are provided. A substrate is provided, and then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.

Abstract translation: 提供Fin-FET和形成Fin-FET的方法。 提供基板，然后在其上形成掩模层。 在衬底和掩模层中形成第一沟槽。 在第一沟槽中形成半导体层。 接下来，去除掩模层，使得半导体层变成嵌入在衬底中并突出在衬底上的散热片结构。 最后，在鳍结构上形成栅极层。

公开(公告)号：US09105720B2

公开(公告)日：2015-08-11

申请号：US14023481

申请日：2013-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Lin ,  An-Chi Liu

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method for manufacturing a semiconductor device having metal gate includes following steps. A substrate having at least a first semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench formed therein. Next, an n-typed work function metal layer is formed in the first gate trench. After forming the n-typed work function metal layer, a nitridation process is performed to form a first protecting layer on the n-typed work function metal layer. After forming the first protecting layer, an oxidation process is performed to the first protecting layer to form a second protecting layer on the n-typed work function metal layer. Then, a gap filling metal layer is formed to fill up the first gate trench.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括以下步骤。 提供了至少形成有第一半导体器件的衬底。 第一半导体器件包括形成在其中的第一栅极沟槽。 接下来，在第一栅极沟槽中形成n型功函数金属层。 在形成n型功函数金属层之后，进行氮化处理以在n型功函数金属层上形成第一保护层。 在形成第一保护层之后，对第一保护层进行氧化处理，以在n型功函数金属层上形成第二保护层。 然后，形成间隙填充金属层以填充第一栅极沟槽。

公开(公告)号：US20150137196A1

公开(公告)日：2015-05-21

申请号：US14592872

申请日：2015-01-08

Applicant: United Microelectronics Corp.

Inventor： Wen-Tai Chiang ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28518 ,  H01L21/28008 ,  H01L21/76804 ,  H01L21/76814 ,  H01L29/41725 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor.

Abstract translation: 本发明提供一种MOS晶体管，其包括衬底，栅极氧化物，栅极，源极/漏极区域和硅化物层。 栅极氧化物设置在衬底上，并且栅极设置在栅极氧化物上。 源极/漏极区域设置在栅极两侧的衬底中。 硅化物层设置在源极/漏极区域上，其中硅化物层包括弯曲的底部表面和弯曲的顶部表面，弯曲的顶部表面和弯曲的底部表面都朝向衬底弯曲，并且弯曲的顶部表面从两个凹陷 侧面，硅化物层尖端的两端在源极/漏极区域上升起，中间的硅化物层比外围的硅化物层厚，从而形成新月形结构。 本发明还提供一种MOS晶体管的制造方法。

公开(公告)号：US20150069533A1

公开(公告)日：2015-03-12

申请号：US14023481

申请日：2013-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Lin ,  An-Chi Liu

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/7833 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method for manufacturing a semiconductor device having metal gate includes following steps. A substrate having at least a first semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench formed therein. Next, an n-typed work function metal layer is formed in the first gate trench. After forming the n-typed work function metal layer, a nitridation process is performed to form a first protecting layer on the n-typed work function metal layer. After forming the first protecting layer, an oxidation process is performed to the first protecting layer to form a second protecting layer on the n-typed work function metal layer. Then, a gap filling metal layer is formed to fill up the first gate trench.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括以下步骤。 提供了至少形成有第一半导体器件的衬底。 第一半导体器件包括形成在其中的第一栅极沟槽。 接下来，在第一栅极沟槽中形成n型功函数金属层。 在形成n型功函数金属层之后，进行氮化处理以在n型功函数金属层上形成第一保护层。 在形成第一保护层之后，对第一保护层进行氧化处理，以在n型功函数金属层上形成第二保护层。 然后，形成间隙填充金属层以填充第一栅极沟槽。

公开(公告)号：US20150017781A1

公开(公告)日：2015-01-15

申请号：US13941208

申请日：2013-07-12

Applicant: United Microelectronics Corp.

Inventor： Chien-Ting Lin ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845

Abstract: A method of forming a shallow trench isolation structure is disclosed. Hard mask patterns are formed on a substrate. A portion of the substrate is removed, using the hard mask patterns as a mask, to form first trenches in the substrate, wherein a fin is disposed between the neighboring first trenches. A filling layer is formed in the first trenches. A patterned mask layer is formed on the filling layer. A portion of the filling layer and a portion of the fins are removed, using the patterned mask layer as a mask, to form second trenches in the substrate. A first insulating layer is formed on the substrate filling in the second trenches.

Abstract translation: 公开了形成浅沟槽隔离结构的方法。 在基板上形成硬掩模图案。 使用硬掩模图案作为掩模去除衬底的一部分，以在衬底中形成第一沟槽，其中翅片设置在相邻的第一沟槽之间。 在第一沟槽中形成填充层。 在填充层上形成图案化掩模层。 使用图案化掩模层作为掩模，去除填充层的一部分和散热片的一部分，以在衬底中形成第二沟槽。 在填充在第二沟槽中的衬底上形成第一绝缘层。

公开(公告)号：US08841197B1

公开(公告)日：2014-09-23

申请号：US13786485

申请日：2013-03-06

Applicant: United Microelectronics Corp.

Inventor： Shih-Hung Tsai ,  Chun-Hsien Lin ,  Chien-Ting Lin

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/461 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/31053 ,  H01L21/76229 ,  H01L29/66795

Abstract: The present invention provides a method for forming a fin structure comprising the following steps: first, a multiple-layer structure is formed on a substrate; then, a sacrificial pattern is formed on the multiple-layer structure, a spacer is formed on the sidewall of the sacrificial pattern and disposed on the multiple-layer structure, the sacrificial pattern is removed, the spacer is used as a cap layer to etch parts of the multiple-layer structure, and then the multiple-layer structure is used as a cap layer to etch the substrate and to form at least one fin structure in the substrate.

Abstract translation: 本发明提供一种形成翅片结构的方法，包括以下步骤：首先，在基板上形成多层结构; 那么，在多层结构上形成牺牲图案，在牺牲图案的侧壁上形成隔离物并且设置在多层结构上，去除牺牲图案，将间隔物用作盖层以蚀刻 多层结构的部分，然后多层结构用作覆盖层以蚀刻基底并在基底中形成至少一个翅片结构。