公开(公告)号：US11902658B2

公开(公告)日：2024-02-13

申请号：US17007347

申请日：2020-08-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Po-Min Wang ,  Yu-Huai Chen

IPC: H04N23/67 ,  G01B11/26 ,  G01B11/02

CPC classification number: H04N23/67 ,  G01B11/026 ,  G01B11/26

Abstract: Systems, apparatuses, and methods for implementing an instant auto-focus mechanism with distance estimation are disclosed. A camera includes at least an image sensor, one or more movement and/or orientation sensors, a timer, a lens, and control circuit. The control circuit receives first and second images captured by the image sensor of a given scene. The control circuit calculates a distance between first and second camera locations when the first and second images, respectively, were captured based on the one or more movement and/or orientation sensors and the timer. Next, the control circuit calculates an estimate of a second distance between the camera and an object in the scene based on the distance between camera locations and angles between the camera and the object from the first and second locations. Then, the control circuit causes the lens to be adjusted to bring the object into focus for subsequent images.

公开(公告)号：US20240045606A1

公开(公告)日：2024-02-08

申请号：US18492081

申请日：2023-10-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JOHNATHAN ALSOP ,  NUWAN JAYASENA ,  SHAIZEEN AGA ,  ANDREW M. MCCRABB

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods and apparatuses to control digital data transfer via a memory channel between a memory module and a processor are disclosed. At least one of the memory module or the processor coalesces a plurality of short data words into multicast coalesced block data comprising a single data block for transfer via the memory channel. Each of the plurality of short data words pertains to one of at least two partitioned memory submodules in the memory module. The multicast coalesced block data is communicated over the memory channel.

公开(公告)号：US11893502B2

公开(公告)日：2024-02-06

申请号：US15849633

申请日：2017-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Nicholas Malaya ,  Nuwan Jayasena

IPC: G06N5/022 ,  G06N20/00 ,  G06F7/02

CPC classification number: G06N5/022 ,  G06N20/00 ,  G06F7/02

Abstract: A system assigns experts of a mixture-of-experts artificial intelligence model to processing devices in an automated manner. The system includes an orchestrator component that maintains priority data that stores, for each of a set of experts, and for each of a set of execution parameters, ranking information that ranks different processing devices for the particular execution parameter. In one example, for the execution parameter of execution speed, and for a first expert, the priority data indicates that a central processing unit (“CPU”) executes the first expert faster than a graphics processing unit (“GPU”). In this example, for the execution parameter of power consumption, and for the first expert, the priority data indicates that a GPU uses less power than a CPU. The priority data stores such information for one or more processing devices, one or more experts, and one or more execution characteristics.

公开(公告)号：US20240037031A1

公开(公告)日：2024-02-01

申请号：US18477351

申请日：2023-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Christopher J. Brennan ,  Akshay Lahiry

IPC: G06F12/06 ,  G06F12/121

CPC classification number: G06F12/0646 ,  G06F12/121

Abstract: A technique for operating a device is disclosed. The technique includes recording log data for the device; analyzing the log data to determine one or more performance settings adjustments to apply to the device; and applying the one or more performance settings adjustments to the device.

公开(公告)号：US20240032270A1

公开(公告)日：2024-01-25

申请号：US18480463

申请日：2023-10-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H10B10/00 ,  G11C7/10 ,  H01L29/423

CPC classification number: H10B10/12 ,  G11C7/1045 ,  H01L29/42392

Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, a memory bit cell uses Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. The memory bit cell includes one of a read bit line and a write word line routed in no other metal layer other than a local interconnect layer. In addition, a six transistor (6T) random access data storage of the given memory bit cell consumes a planar area above a silicon substrate of four transistors.

公开(公告)号：US11880715B2

公开(公告)日：2024-01-23

申请号：US17222543

申请日：2021-04-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Nicholas Malaya ,  Yasuko Eckert

IPC: G06F9/50 ,  G06N3/082

CPC classification number: G06F9/5044 ,  G06F9/505 ,  G06F9/5066 ,  G06N3/082

Abstract: Methods and systems for load balancing in a neural network system using metadata are disclosed. Any one or a combination of one or more kernels, one or more neurons, and one or more layers of the neural network system are tagged with metadata. A scheduler detects whether there are neurons that are available to execute. The scheduler uses the metadata to schedule and load balance computations across compute resources and available resources.

公开(公告)号：US11880312B2

公开(公告)日：2024-01-23

申请号：US17539189

申请日：2021-11-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Kishore Punniyamurthy ,  SeyedMohammad SeyedzadehDelcheh ,  Sergey Blagodurov ,  Ganesh Dasika ,  Jagadish B Kotra

IPC: G06F12/00 ,  G06F12/126 ,  G06F12/0855

CPC classification number: G06F12/126 ,  G06F12/0859 ,  G06F2212/1024 ,  G06F2212/6042

Abstract: A method includes storing a function representing a set of data elements stored in a backing memory and, in response to a first memory read request for a first data element of the set of data elements, calculating a function result representing the first data element based on the function.

公开(公告)号：US11880310B2

公开(公告)日：2024-01-23

申请号：US17553044

申请日：2021-12-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Paul Moyer ,  John Kelley

IPC: G06F12/12

CPC classification number: G06F12/12 ,  G06F2212/601

Abstract: A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.

公开(公告)号：US11875875B2

公开(公告)日：2024-01-16

申请号：US17564426

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani

IPC: G11C7/22 ,  G11C7/10 ,  G11C5/06

CPC classification number: G11C7/222 ,  G11C5/06 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/1093

Abstract: Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the training of the interface, techniques disclosed comprise generating a training clock from the clock signal at the first pulse rate, the training clock having a clock signal at a second pulse rate, and sending, based on the generated training clock, command signals, including address data, to the DRAM.

公开(公告)号：US11875197B2

公开(公告)日：2024-01-16

申请号：US17136738

申请日：2020-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Bradford Michael Beckmann ,  Steven Tony Tye ,  Brian L. Sumner ,  Nicolai Hähnle

IPC: G06F9/38 ,  G06F9/52 ,  G06T1/20 ,  G06F9/30

CPC classification number: G06F9/52 ,  G06F9/30141 ,  G06F9/3836 ,  G06T1/20

Abstract: Systems, apparatuses, and methods for managing a number of wavefronts permitted to concurrently execute in a processing system. An apparatus includes a register file with a plurality of registers and a plurality of compute units configured to execute wavefronts. A control unit of the apparatus is configured to allow a first number of wavefronts to execute concurrently on the plurality of compute units. The control unit is configured to allow no more than a second number of wavefronts to execute concurrently on the plurality of compute units, wherein the second number is less than the first number, in response to detection that thrashing of the register file is above a threshold. The control unit is configured to detect said thrashing based at least in part on a number of registers in use by executing wavefronts that spill to memory.