Abstract:
A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. In the lattice-like delay circuit, input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of a plurality of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.
Abstract:
A focus adjustment mechanism upon assembly of an AF compact camera includes a shutter having a focusing lens frame which is screw-engaged therein, and a ring-shaped connecting member with an arm to be engaged with an AF driving lever of the shutter and to be fixed to the lens frame. The lens frame is provided with a cylindrical engagement surface to which the ring-shaped connecting member is engaged from the front end thereof and a plurality of engaging portions to be engaged with an adjuster for rotation of the lens frame. The adjuster comprises a plurality of corresponding engaging portions to rotate the lens frame.
Abstract:
A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.
Abstract:
A dielectric ceramic composition of the invention comprises as major components 94 to 99 mol % of barium titanate, calculated as BaTiO.sub.3, 0.05 to 3 mol % of tantalum oxide, calculated as Ta.sub.2 O.sub.5, 0.05 to 3 mol % of niobium oxide, calculated as Nb.sub.2 O.sub.5, and 0.5 to 3 mol % of zinc oxide, calculated as ZnO, and further contains as a subordinate additive at least one of calcium zirconate, strontium zirconate and barium zirconate in a total amount of 0.2 to 5% by weight per 100 mol % of said major components, calculated as CaZrO.sub.3, SrZrO.sub.3 and BaZrO.sub.3, respectively. The dielectric ceramic composition having a high dielectric constant is most unlikely to delaminate and is suitable for a multilayered ceramic capacitor. This dielectric ceramic composition has also little, if any, capacitance change and dielectric loss over a wide temperature range of -55.degree. C. to +150.degree. C.
Abstract:
A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.
Abstract:
In a waterproof lens barrel in which a water-tight movable barrel which moves in the optical a is direction includes inner and outer cylinders, and a space between the inner and outer cylinders is sealed by an annular seal member, the annular seal member is held by a seal member holding ring separate from the inner cylinder or the outer cylinder. The seal member holding ring is inserted in the outer cylinder, wherein the annular seal member is brought into elastic contact with the inner surface of the outer cylinder. The inner cylinder is fitted in and secured to the outer cylinder, wherein the seal member holding ring is located in front of the inner cylinder.
Abstract:
In a connecting mechanism which connects two members, one of the two members is provided with an elastically deformable engaging portion, and the other member is provided with a contact surface which is brought into contact with the elastically deformable engaging portion, which is elastically deformed at a front end. The two members are engaged with each other by elastically deforming the elastically deformable engaging portion so that the latter comes into contact with the contact surface. The elastically deformable engaging portion and the contact surface are shaped such that the engagement force of the two members during a connecting operation is stronger than the engagement force when the connecting operation is completed.
Abstract:
A flexible printed circuit board supporting structure for mounting a flexible printed circuit board in a restricted space without using an exclusive member to support the flexible printed circuit board. A lens barrel includes a fixed lens barrel integrally secured to a camera body and a movable lens barrel positioned in the fixed lens barrel and movable in the direction of the optical axis. An electrically driven device such as a shutter is mounted to the movable lens barrel and a controller for the electrically driven device is mounted to the camera body. A flexible printed circuit board electrically connects the controller to the electrically driven device. The flexible printed circuit board is connected to the electrically driven device and is extracted toward the rear of a camera in the movable lens barrel. The flexible printed circuit board also extends toward the front of the camera in a space formed between the fixed lens barrel and the movable lens a barrel and is drawn out of the fixed lens barrel from the front portion thereof. The flexible printed circuit board is supported in a space formed by the outer periphery of a light intercepting member which is disposed between the fixed lens barrel and the movable lens barrel, and the inner peripheral portion of the fixed lens barrel.
Abstract:
In a voltage converter which is disposed in a semiconductor integrated circuit so as to lower an external supply voltage and to feed the lowered voltage to a partial circuit of the integrated circuit; the voltage converter is constructed so as to produce an output voltage suited to an ordinary operation in the ordinary operation state of the semiconductor integrated circuit and an aging voltage in the aging test of the circuit.
Abstract:
The present invention is intended to operate a semiconductor device at high speed with low voltage. A circuit configuration is used in which the transfer impedance between a common I/O line and a data line is changed depending on whether information is to be read or written. A current/voltage converter is provided which includes a MISFET different in conduction type to a select MISFET. Thus, the speed of reading information is increased. An intermediate voltage generator having high driving capability is provided. Thus, the circuit has sufficient driving capability for an LSI having large load capacitance. A voltage converter is provided which converts a data line supply voltage or word line supply voltage to a higher voltage. Therefore, stabilized signal transmission is ensured.