公开(公告)号：US09570032B2

公开(公告)日：2017-02-14

申请号：US14855932

申请日：2015-09-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hajime Kimura ,  Atsushi Umezaki

IPC: G06F3/038 ,  G09G3/36

CPC classification number: G09G3/3688 ,  G09G3/3607 ,  G09G3/3655 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2320/0673 ,  G09G2320/068 ,  G09G2330/023

Abstract: A liquid crystal display device includes a pixel having a first to nth (n is a natural number of 2 or more) subpixels and a circuit. To the circuit, N (N is a natural number of 2 or more) wirings for supplying a digital signal with N bits and first to nth wiring groups having M (M is a natural number of 2 or more) wirings for supplying M different voltages are electrically connected. The liquid crystal display device has a function of converting the digital signal into n analog signals by using the M voltages supplied to the first to nth wiring groups and inputting the n analog signals to first to nth subpixels. The first to nth subpixels each include an electrode for driving a liquid crystal element.

Abstract translation: 液晶显示装置包括具有第一至第n（n为2以上的自然数）子像素的像素和电路。 对于电路，N（N是2或更多个的自然数）布线，用于向具有N位的数字信号和具有M（M为2或更多个的自然数）的第n至第n布线组提供M个不同电压的数字信号 电连接。 液晶显示装置具有通过使用提供给第一至第N布线组的M个电压并将n个模拟信号输入到第一至第N子像素而将数字信号转换为n个模拟信号的功能。 第一至第n子像素包括用于驱动液晶元件的电极。

公开(公告)号：US20160238916A1

公开(公告)日：2016-08-18

申请号：US15140577

申请日：2016-04-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G02F1/1362 ,  G02F1/1368 ,  G11C19/28 ,  G09G3/36 ,  H01L27/12 ,  H01L27/15 ,  G02F1/133 ,  G02F1/1345

CPC classification number: G02F1/136286 ,  G02F1/13306 ,  G02F1/133753 ,  G02F1/13452 ,  G02F1/136213 ,  G02F1/1368 ,  G02F1/1393 ,  G02F2001/133622 ,  G02F2202/103 ,  G09G3/342 ,  G09G3/3655 ,  G09G3/3674 ,  G09G3/3677 ,  G09G3/3685 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2310/024 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0252 ,  G09G2330/021 ,  G11C19/28 ,  H01L21/67167 ,  H01L27/06 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/15 ,  H01L27/156 ,  H01L27/3211 ,  H01L27/3213 ,  H01L27/3216 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L29/247 ,  H01L29/78693 ,  H01L51/5246 ,  H01L51/56 ,  H01L2251/5307 ,  H01L2251/5315 ,  H01L2251/5323

Abstract: A first transistor, a second transistor, a third transistor, a fourth transistor are provided. In the first transistor, a first terminal is electrically connected to a first wiring; a second terminal is electrically connected to a gate terminal of the second transistor; a gate terminal is electrically connected to a fifth wiring. In the second transistor, a first terminal is electrically connected to a third wiring; a second terminal is electrically connected to a sixth wiring. In the third transistor, a first terminal is electrically connected to a second wiring; a second terminal is electrically connected to the gate terminal of the second transistor; a gate terminal is electrically connected to a fourth wiring. In the fourth transistor, a first terminal is electrically connected to the second wiring; a second terminal is electrically connected to the sixth wiring; a gate terminal is connected to the fourth wiring.

公开(公告)号：US09362412B2

公开(公告)日：2016-06-07

申请号：US13975422

申请日：2013-08-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G3/36 ,  H01L29/786 ,  G09G3/20

CPC classification number: H01L29/7869 ,  G09G3/20 ,  G09G3/3648 ,  G09G2300/04 ,  G09G2310/0275 ,  G11C19/28 ,  H01L21/477 ,  H01L27/1255 ,  H01L27/127

Abstract: One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.

公开(公告)号：US09337184B2

公开(公告)日：2016-05-10

申请号：US14552547

申请日：2014-11-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Atsushi Umezaki

IPC: G02F1/136 ,  H01L27/06 ,  G02F1/1362 ,  G09G3/36 ,  G09G3/32 ,  G09G3/34

CPC classification number: H01L27/1255 ,  G02F1/134309 ,  G02F1/13624 ,  G02F1/136286 ,  G02F1/1368 ,  G09G3/3266 ,  G09G3/3413 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2310/0235 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0252 ,  G09G2330/021 ,  G11C19/28 ,  H01L27/0629 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L29/78663 ,  H01L29/78672 ,  H01L29/7869

Abstract: It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed.

Abstract translation: 本发明的目的是减少连接到电容器的晶体管的数量。 在结构中，包括电容器和一个晶体管，电容器的一个电极连接到布线，并且电容器的另一个电极连接到晶体管的栅极。 由于时钟信号被输入到布线，所以通过电容将时钟信号输入到晶体管的栅极。 然后，通过与时钟信号同步的信号来控制晶体管的导通/截止，从而重复晶体管导通的周期和晶体管截止的周期。 以这种方式，可以抑制晶体管的劣化。

公开(公告)号：US09070593B2

公开(公告)日：2015-06-30

申请号：US13675066

申请日：2012-11-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: H03K19/0175 ,  H01L27/12 ,  G09G3/36 ,  G09G3/20 ,  H01L21/84 ,  G02F1/1368 ,  H01L27/15

CPC classification number: H01L27/124 ,  G02F1/13306 ,  G02F1/13624 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136245 ,  G09G3/20 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/04 ,  G09G2300/08 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/08 ,  H01L21/84 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/156 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78696

Abstract: To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

Abstract translation: 提供用于移位寄存器等的电路。 基本配置包括第一至第四晶体管和四个布线。 电源电位VDD被提供给第一布线，电源电位VSS被提供给第二布线。 向第三布线和第四布线中的每一个提供二进制数字信号。 数字信号的H电平等于电源电位VDD，数字信号的L电平等于电源电位VSS。 第三布线和第四布线的电位有四种组合。 第一晶体管至第四晶体管中的每一个可通过电势的任意组合而被关断。 也就是说，由于不存在恒定导通的晶体管，因此可以抑制晶体管的特性的劣化。

公开(公告)号：US09070546B2

公开(公告)日：2015-06-30

申请号：US13968593

申请日：2013-08-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: H03K3/00 ,  H01L25/00 ,  G11C19/28 ,  G02F1/1362 ,  H01L27/12

CPC classification number: H01L25/00 ,  G02F1/1362 ,  G09G3/3677 ,  G09G2310/0286 ,  G11C19/28 ,  H01L27/1225 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device in which change in characteristics of a transistor is suppressed and an output signal is changed sharply without increasing W/L of the transistor can be provided. Two transistors are connected in parallel between a wiring to which a low potential is supplied and an output terminal. When the low potential is output from the output terminal, both of the two transistors are turned on and then one of them is turned off. Thus, change in characteristics of the transistor can be suppressed and an output signal can be changed sharply without increasing W/L of the transistor.

Abstract translation: 提供了可以提供晶体管的特性变化抑制输出信号急剧变化而不增加晶体管的W / L的半导体器件。 在提供低电位的布线和输出端子之间并联连接两个晶体管。 当从输出端子输出低电位时，两个晶体管都导通，然后其中一个截止。 因此，可以抑制晶体管的特性变化，并且输出信号可以在不增加晶体管的W / L的情况下急剧变化。

公开(公告)号：US20150137118A1

公开(公告)日：2015-05-21

申请号：US14548365

申请日：2014-11-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki ,  Hiroyuki Miyake

IPC: H01L27/12

CPC classification number: H01L27/124 ,  G09G3/2092 ,  G09G3/3266 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0205 ,  G09G2310/0248 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2310/061 ,  G09G2320/0646 ,  G09G2320/0666 ,  G11C19/28 ,  H01L27/0207 ,  H01L27/1222 ,  H01L27/1225

Abstract: To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

Abstract translation: 为了抑制晶体管的阈值电压的波动，为了减少显示面板和驱动器IC的连接数量，为了实现显示装置的功耗的降低，并且实现显示装置的尺寸和高清晰度的增加 。 容易恶化的晶体管的栅电极通过第一开关晶体管和通过第二开关晶体管供给低电位的布线而连接到提供高电位的布线; 时钟信号被输入到第一开关晶体管的栅电极; 并且反相时钟信号被输入到第二开关晶体管的栅电极。 因此，高电位和低电位交替施加到容易劣化的晶体管的栅电极。

公开(公告)号：US09036766B2

公开(公告)日：2015-05-19

申请号：US13775854

申请日：2013-02-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G11C19/00 ,  G11C19/28 ,  H01L27/088 ,  H01L27/32 ,  H01L27/12

CPC classification number: G11C19/28 ,  G09G3/2092 ,  G09G2310/0267 ,  G09G2310/0286 ,  H01L27/088 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/156 ,  H01L27/3244 ,  H01L29/7869

Abstract: A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

Abstract translation: 提供了移位低电平信号的半导体器件。 在一个示例中，第一晶体管包括电连接到第一布线的第一端子和电连接到第二布线的第二端子，第二晶体管，包括电连接到第三布线的第一端子和与第二布线电连接的第二端子 布线，第三晶体管，包括电连接到第四布线的第一端子和电连接到第二晶体管的栅极的第二端子;第四晶体管，包括电连接到第五布线的第一端子，电连接到第二布线的第二端子， 第三晶体管的栅极和电连接到第六布线的栅极，以及包括电连接到第三布线的第一端子和电连接到第一晶体管的栅极的第二端子的第一开关。

公开(公告)号：US20150042918A1

公开(公告)日：2015-02-12

申请号：US14522792

申请日：2014-10-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Atsushi Umezaki

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/12

CPC classification number: G09G3/3677 ,  G02F1/13624 ,  G02F1/1368 ,  G02F2202/10 ,  G09G3/20 ,  G09G3/3674 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2300/0809 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2330/021 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/7869

Abstract: A driver circuit includes a circuit 200, a transistor 101—1, and a transistor 101—2. A signal is selectively input from the circuit 200 to a gate of the transistor 101—1 and the transistor 101—2, so that the transistor 101—1 and the transistor 101—2 are controlled to be on or off. The transistor 101—1 and the transistor 101—2 are turned on or off, thus, the wiring 112 and the wiring 111 become conducting or non-conducting.

Abstract translation: 驱动器电路包括电路200，晶体管101-1和晶体管101-2。 从电路200选择性地输入信号到晶体管101-1和晶体管101-2的栅极，使得晶体管101-1和晶体管101-2被控制为导通或截止。 晶体管101-1和晶体管101-2导通或截止，因此布线112和布线111变为导通或不导通。

公开(公告)号：US08872572B2

公开(公告)日：2014-10-28

申请号：US14147647

申请日：2014-01-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun Koyama ,  Atsushi Umezaki

IPC: H03L5/00 ,  H03K19/00 ,  H03K17/687 ,  H03K19/0185 ,  H01L27/12

CPC classification number: G09G3/3677 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/00 ,  H01L27/0207 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H03K17/687 ,  H03K19/0013 ,  H03K19/018557 ,  H03K19/018571

Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.