公开(公告)号：US08969168B2

公开(公告)日：2015-03-03

申请号：US13809473

申请日：2012-01-30

Applicant: Takeki Ninomiya ,  Yukio Hayakawa ,  Takumi Mikawa ,  Takeshi Takagi

Inventor： Takeki Ninomiya ,  Yukio Hayakawa ,  Takumi Mikawa ,  Takeshi Takagi

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/1641 ,  G11C13/0007 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1675

Abstract: Provided is a method for manufacturing a variable resistance element, the method including: forming a first electrode material layer above a substrate; forming a first tantalum oxide material layer; forming a second tantalum oxide material layer; forming a second electrode material layer; and annealing at least the first tantalum oxide material layer after forming the first tantalum oxide material layer and before forming the second electrode material layer, wherein an oxygen content percentage of one of the first tantalum oxide material layer and the second tantalum oxide material layer is higher than an oxygen content percentage of the other.

Abstract translation: 提供一种制造可变电阻元件的方法，该方法包括：在衬底上形成第一电极材料层; 形成第一钽氧化物材料层; 形成第二钽氧化物材料层; 形成第二电极材料层; 以及在形成所述第一钽氧化物材料层之后并且在形成所述第二电极材料层之前至少退火所述第一钽氧化物材料层，其中所述第一钽氧化物材料层和所述第二氧化钽材料层中的一个的氧含量百分比较高 比另一个的氧含量百分比。

公开(公告)号：US08675393B2

公开(公告)日：2014-03-18

申请号：US13636258

申请日：2011-03-18

Applicant: Koji Katayama ,  Takeshi Takagi ,  Mitsuteru Iijima

Inventor： Koji Katayama ,  Takeshi Takagi ,  Mitsuteru Iijima

IPC: G11C11/00

CPC classification number: G11C13/0007 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

Abstract: Provided is a method for driving a non-volatile memory element in which a variable resistance element including a first electrode, a second electrode, and a variable resistance layer capable of reversibly changing between a high resistance state and a low resistance state with application of electrical signals having different polarities is connected in series with a current steering element having bidirectional rectifying characteristics with respect to an applied voltage. After the non-volatile memory element is manufactured, the resistance value of the variable resistance layer is reduced from a resistance value in the initial resistance state higher than that in the high resistance state by applying, to the non-volatile memory element, a voltage pulse having the polarity identical to that of the voltage pulse for changing the variable resistance layer from the low resistance state to the high resistance state in the normal operations.

Abstract translation: 提供一种用于驱动非易失性存储元件的方法，其中包括第一电极，第二电极和可变电阻层的可变电阻元件，所述可变电阻元件能够通过施加电而在高电阻状态和低电阻状态之间可逆地变化 具有不同极性的信号与具有相对于施加电压的双向整流特性的电流导向元件串联连接。 在制造非易失性存储元件之后，通过向非易失性存储元件施加电压，可变电阻层的电阻值比初始电阻状态中的电阻值高于高电阻状态的电阻值 脉冲具有与用于在正常操作中将可变电阻层从低电阻状态改变为高电阻状态的电压脉冲的极性相同的脉冲。

公开(公告)号：US20130314975A1

公开(公告)日：2013-11-28

申请号：US13983855

申请日：2012-02-07

Applicant: Koji Katayama ,  Takeshi Takagi

Inventor： Koji Katayama ,  Takeshi Takagi

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/004 ,  G11C29/50008 ,  G11C2013/0045 ,  G11C2013/0083 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2418 ,  H01L28/20 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: A method for programming a nonvolatile memory element includes: decreasing a resistance value of a variable resistance element in an initial state, by applying an initialization voltage pulse to a series circuit in which a load resistor having a first resistance value is connected in series with the variable resistance element and a MSM diode; applying, after the decreasing, a write voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a second resistance value lower than the first resistance value; and applying, after the decreasing, an erase voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a third resistance value lower than the first resistance value.

Abstract translation: 一种用于非易失性存储元件的编程方法包括：通过向串联电路施加初始化电压脉冲来降低初始状态下的可变电阻元件的电阻值，其中具有第一电阻值的负载电阻器与 可变电阻元件和MSM二极管; 在可变电阻元件的电阻值变为低于第一电阻值的第二电阻值之后，在减小之后向串联电路施加写入电压脉冲; 以及在所述可变电阻元件的电阻值变为低于所述第一电阻值的第三电阻值之后，在所述减小之后向所述串联电路施加擦除电压脉冲。

公开(公告)号：US08508976B2

公开(公告)日：2013-08-13

申请号：US12994910

申请日：2010-04-23

Applicant: Koji Katayama ,  Takeshi Takagi

Inventor： Koji Katayama ,  Takeshi Takagi

IPC: G11C11/00 ,  H01L45/00

CPC classification number: G11C13/003 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/56 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1683

Abstract: Provided is a nonvolatile memory element which has a small variation in operation and allow stable operation. The nonvolatile memory element includes: a first electrode (102); a second electrode (106); a variable resistance layer (105) which is formed between the electrodes (102 and 106) and is connected to the electrodes (102 and 106), and which reversibly changes between a high resistance state and a low resistance state according to a polarity of a voltage applied between the electrodes (102 and 106); and a fixed resistance layer (104) which has a resistance value that is 0.1 and 10 times as large as a resistance value of the variable resistance layer in the high resistance state, the fixed resistance layer (104) being formed between the electrodes (102 and 106) and being electrically connected to at least a part of the variable resistance layer (105).

Abstract translation: 提供了一种非易失性存储元件，其具有小的操作变化并且允许稳定的操​​作。 非易失性存储元件包括：第一电极（102）; 第二电极（106）; 形成在所述电极（102和106）之间并连接到所述电极（102和106）的可变电阻层（105），并且根据所述电极（102和106）的极性在高电阻状态和低电阻状态之间可逆地变化 施加在电极（102和106）之间的电压; 和固定电阻层（104），其电阻值是高电阻状态下的可变电阻层的电阻值的0.1和10倍，固定电阻层（104）形成在电极（102）之间 和106），并且电连接到可变电阻层（105）的至少一部分。

公开(公告)号：US08391051B2

公开(公告)日：2013-03-05

申请号：US13001840

申请日：2010-04-09

Applicant: Yoshihiko Kanzawa ,  Takeshi Takagi

Inventor： Yoshihiko Kanzawa ,  Takeshi Takagi

IPC: G11C11/00

CPC classification number: G11C13/0011 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2213/34 ,  G11C2213/79

Abstract: Provided is a programming method for improving the retention characteristics of information in a variable resistance nonvolatile memory element. The method includes: a first writing process of applying a first voltage V1 having a first polarity to set the variable resistance nonvolatile storage element to a low resistance state LR indicating first logic information (S01); a second writing process of applying a second voltage V2 having a second polarity different from the first polarity to set the variable resistance nonvolatile storage element to a first high resistance state HR1 (S02); and a partial write process of applying a third voltage V3 having the first polarity so as to set the variable resistance layer to a second high resistance state HR2 indicating second logic information different from the first logic information (S05). Here, |V3|

Abstract translation: 提供了一种用于改善可变电阻非易失性存储元件中的信息的保持特性的编程方法。 该方法包括：施加具有第一极性的第一电压V1的第一写入处理将可变电阻非易失性存储元件设置为指示第一逻辑信息的低电阻状态LR（S01）; 第二写入处理，施加具有与第一极性不同的第二极性的第二电压V2，以将可变电阻非易失性存储元件设置为第一高电阻状态HR1（S02）; 以及施加具有第一极性的第三电压V3以便将可变电阻层设置为指示与第一逻辑信息不同的第二逻辑信息的第二高电阻状态HR2的部分写入处理（S05）。 这里，| V3 | <| V1 |，HR1，HR2，LR中的电阻值依次较大。

公开(公告)号：US08309946B2

公开(公告)日：2012-11-13

申请号：US12935455

申请日：2009-07-22

Applicant: Satoru Mitani ,  Shunsaku Muraoka ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Ryoko Miyanaga ,  Satoru Fujii ,  Takeshi Takagi

Inventor： Satoru Mitani ,  Shunsaku Muraoka ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Ryoko Miyanaga ,  Satoru Fujii ,  Takeshi Takagi

IPC: H01L47/00

CPC classification number: H01L27/101 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

Abstract: A resistance variable element of the present invention comprises a first electrode (103), a second electrode (107), and a resistance variable layer which is interposed between the first electrode (103) and the second electrode (107) to contact the first electrode (103) and the second electrode (107), the resistance variable layer being configured to change in response to electric signals with different polarities which are applied between the first electrode (103) and the second electrode (107), the resistance variable layer comprising an oxygen-deficient transition metal oxide layer, and the second electrode (107) comprising platinum having minute hillocks (108).

Abstract translation: 本发明的电阻可变元件包括第一电极（103），第二电极（107）和介于第一电极（103）和第二电极（107）之间的电阻变化层，以接触第一电极 （103）和第二电极（107），电阻变化层被配置为响应于施加在第一电极（103）和第二电极（107）之间的具有不同极性的电信号而改变，电阻变化层包括 氧缺乏的过渡金属氧化物层，以及包含具有分开的小丘（108）的铂的第二电极（107）。

公开(公告)号：US20120170353A1

公开(公告)日：2012-07-05

申请号：US13379463

申请日：2011-06-28

Applicant: Mitsuteru Iijima ,  Takeshi Takagi ,  Koji Katayama

Inventor： Mitsuteru Iijima ,  Takeshi Takagi ,  Koji Katayama

IPC: G11C11/00

CPC classification number: G11C13/003 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: A method for programming a nonvolatile memory device according to the present invention includes a step of detecting an excessively low resistance cell from among a plurality of memory cells (11) (S101); a step of changing the resistance value of a load resistor (121) to a second resistance value smaller than a first resistance value (S103); and a step of causing, by applying a voltage pulse to a series circuit including the excessively low resistance cell and the load resistor (121) having the second resistance value, a variable resistance element (105) included in the excessively low resistance cell to shift to a second high resistance state having a resistance value greater than that of the first low resistance state (S104).

Abstract translation: 根据本发明的非易失性存储器件的编程方法包括从多个存储单元（11）中检测过低电阻单元的步骤（S101）; 将负载电阻器（121）的电阻值改变为小于第一电阻值的第二电阻值的步骤（S103）; 以及通过对包括过低电阻单元的串联电路和具有第二电阻值的负载电阻器（121）施加电压脉冲，使包含在过低电阻单元中的可变电阻元件（105）移位 到具有大于第一低电阻状态的电阻值的第二高电阻状态（S104）。

公开(公告)号：US08179713B2

公开(公告)日：2012-05-15

申请号：US12671162

申请日：2009-05-18

Applicant: Yoshihiko Kanzawa ,  Satoru Mitani ,  Zhiqiang Wei ,  Takeshi Takagi

Inventor： Yoshihiko Kanzawa ,  Satoru Mitani ,  Zhiqiang Wei ,  Takeshi Takagi

IPC: G11C11/00

CPC classification number: H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2418 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

Abstract: A nonvolatile memory element comprises a first electrode (103), a second electrode (105), and a resistance variable layer (104) which is provided between the first electrode and the second electrode, and is configured to reversibly switch an interelectrode resistance value which is a resistance value between the first electrode and the second electrode, in response to an interelectrode voltage which is an electric potential of the second electrode on the basis of the first electrode, the resistance variable layer includes an oxygen-deficient transition metal oxide, the first electrode side and the second electrode side have an asymmetric structure, a portion of the resistance variable layer which is located at the first electrode side and a portion of the resistance variable layer which is located at the second electrode side are each configured to be selectively placed into one of a low-resistance state and a high-resistance state, so as to attain a stable state in three or more different interelectrode resistance values, the stable state being a state in which the interelectrode resistance value is invariable regardless of a change in the interelectrode voltage within a specified range.

Abstract translation: 非易失性存储元件包括设置在第一电极和第二电极之间的第一电极（103），第二电极（105）和电阻变化层（104），并且被配置为可逆地切换电极间电阻值， 是第一电极和第二电极之间的电阻值，响应于基于第一电极的第二电极的电位的电极间电压，电阻变化层包括缺氧过渡金属氧化物， 第一电极侧和第二电极侧具有不对称结构，位于第一电极侧的电阻变化层的一部分和位于第二电极侧的电阻变化层的一部分分别构成为选择性地 放置成低电阻状态和高电阻状态之一，以达到三个或更多个差异的稳定状态 出现电极间电阻值，稳定状态是不管电极间电压在规定范围内的变化如何，电极间电阻值不变的状态。

公开(公告)号：US08148711B2

公开(公告)日：2012-04-03

申请号：US12600793

申请日：2008-05-16

Applicant: Satoru Fujii ,  Yoshihiko Kanzawa ,  Takeshi Takagi ,  Kazuhiko Shimakawa

Inventor： Satoru Fujii ,  Yoshihiko Kanzawa ,  Takeshi Takagi ,  Kazuhiko Shimakawa

IPC: H01L45/00

CPC classification number: H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/1625

Abstract: A nonvolatile semiconductor apparatus of the present invention comprises (103), a second electrode (105), and a resistance variable layer (104) disposed between the first electrode (103) and the second electrode (105), a resistance value of the resistance variable layer being switchable reversibly in response to an electric signal applied between the electrodes (103), (105), wherein the resistance variable layer (104) comprises an oxide containing tantalum and nitrogen.

Abstract translation: 本发明的非易失性半导体装置包括：（103），设置在第一电极（103）和第二电极（105）之间的第二电极（105）和电阻变化层（104），电阻值 可变层可响应施加在电极（103），（105）之间的电信号而可逆地切换，其中电阻变化层（104）包括含有钽和氮的氧化物。

公开(公告)号：US08125817B2

公开(公告)日：2012-02-28

申请号：US12867392

申请日：2009-12-16

Applicant: Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

Inventor： Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

IPC: G11C11/00 ,  G11C5/06 ,  G11C11/34 ,  G11C5/14 ,  G11C7/00

CPC classification number: H01L27/101 ,  G11C13/0002 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

Abstract: To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . .) each of which is provided at three-dimensional cross-points between word lines (WL0, WL1, . . .) and bit lines (BL0, BL1, . . .) and having a resistance value that reversibly changes based on an electrical signal; a row selection circuit-and-driver (103) provided with transistors (103a) each of which applies a predetermined voltage to a corresponding one of the word lines (WL0, WL1, . . .); a column selection circuit-and-driver (104) provided with transistors (104a) each of which applies a predetermined voltage to a corresponding one of the bit lines (BL0, BL1, . . .); and a substrate bias circuit (110) which applies a forward bias voltage to a substrate of such transistors (103a and 104a).

Abstract translation: 提供能够实现稳定操作并且包括可变电阻元件的非易失性存储装置（100）。 非易失性存储装置（100）包括：存储单元（M111，M112 ...），每个存储单元设置在字线（WL0，WL1 ...）与位线（BL0， BL1，...），并且具有基于电信号可逆地改变的电阻值; 具有晶体管（103a）的行选择电路驱动器（103），每个晶体管将预定电压施加到对应的一个字线（WL0，WL1 ...）; 具有晶体管（104a）的列选择电路驱动器（104），每个晶体管将预定电压施加到相应的位线（BL0，BL1 ...）中; 以及向这种晶体管（103a和104a）的衬底施加正向偏置电压的衬底偏置电路（110）。