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公开(公告)号：US09430386B2
公开(公告)日：2016-08-30
申请号：US14217436
申请日：2014-03-17
Applicant: BiTMICRO Networks, Inc.
Inventor： Rolando H. Bruce , Elmer Paule Dela Cruz , Mark Ian Alcid Arcedera
IPC: G06F12/08
CPC classification number: G06F12/0811 , G06F12/0844 , G06F12/0868 , G06F2212/1016 , G06F2212/217 , G06F2212/225 , G06F2212/313
Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower. Methods provided here may be extended for systems that have more than two cache levels.
Abstract translation: 描述了具有包括旋转驱动器，闪存装置，SDRAM和SRAM的不同类型的存储装置的混合的混合存储系统。 旋转驱动器用作主存储器，提供每单位存储存储器的最低成本。 闪存用作旋转驱动器的更高级缓存。 提供了用于管理该存储系统的多级缓存的方法，其具有由易失性存储器（SRAM或SDRAM）组成的非常快速的1级缓存以及使用闪存器件阵列的非易失性级别2高速缓存。 它描述了一种在旋转驱动器之间分配数据以使缓存更有效率的方法。 它还描述了将数据从L1高速缓存和L2高速缓存冲刷到旋转驱动器的有效技术，利用并发闪存设备操作，并发旋转驱动操作和最大化旋转驱动器中的顺序访问类型，而不是相对较慢的随机访问。 这里提供的方法可以扩展到具有两个以上缓存级别的系统。
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公开(公告)号：US20140289441A1
公开(公告)日：2014-09-25
申请号：US14297628
申请日：2014-06-06
Applicant: BiTMICRO Networks, Inc.
IPC: G06F13/16
CPC classification number: G06F13/1657 , G06F12/00 , G06F12/0246 , G06F13/1673 , G06F13/1684 , G06F13/36
Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.
Abstract translation: 本发明涉及用于在至少一个DMA控制器与至少一个固态半导体存储器件（诸如NAND闪存器件等）之间传送信息的多电平存储器总线系统。 该多电平存储器总线系统包括耦合到中间总线的至少一个DMA控制器; 闪存总线; 以及中间总线和闪存总线之间的闪存缓冲电路。 该多级存储器总线系统可以被设置为支持：n位宽的总线宽度，例如半字节宽度或字节宽度的总线宽度; 中间总线上的可选择的数据采样率，例如单次或双次采样率; 可配置的总线数据速率，例如单，双，四进制或八进制数据采样率; CRC保护; 独家繁忙的机制; 专线忙 或这些的任何组合。
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公开(公告)号：US10430303B1
公开(公告)日：2019-10-01
申请号：US15891147
申请日：2018-02-07
Applicant: BITMICRO Networks, Inc.
Abstract: In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.
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公开(公告)号：US10120694B2
公开(公告)日：2018-11-06
申请号：US14217365
申请日：2014-03-17
Applicant: BiTMICRO Networks, Inc.
Inventor： Alvin Anonuevo Manlapat , Ian Victor Pasion Beleno
IPC: G06F1/24 , G06F9/44 , G06F9/4401 , G06F1/12
Abstract: A mechanism of booting up a system directly from a storage device and a means of initializing an embedded system prior to activating a CPU is presented. The said system is comprised of one or more CPUs, a reset controller, a storage device controller, one or more direct memory access controllers, a RAM and its controller, a ROM and its controller, a debug interface and a power-on reset (POR) sequencer. The POR sequencer controls the overall boot process of the embedded system. Said sequencer uses descriptors (POR Sequencer descriptors) which are used to update the configuration registers of the system and to enable CPU-independent data transfers with the use of DMA controllers.Using a minimal amount of non-volatile memory for booting up a system brings down costs associated with increased silicon real estate area and power consumption. Capability of pre-initializing the system even before a CPU is brought out of reset provides flexibility and system robustness. Through the use of the Power-On Reset Sequencer module, integrity of program code and user data used in the boot up process can be verified thus providing a resilient boot up sequence.The present invention provides a mechanism for booting up a system using a minimum amount of nonvolatile memory. This method also enables the embedded system to initialize all configuration registers even before any of the CPUs of the system is brought out of reset. The embedded system consists of multiple controller chips or a single controller chip. The embedded system can have a single or multiple central processing units.
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公开(公告)号：US10078604B1
公开(公告)日：2018-09-18
申请号：US14690349
申请日：2015-04-17
Applicant: BiTMICRO Networks, Inc.
Inventor： Arnaldo Cristobal , Marlon Verdan
CPC classification number: G06F13/24 , G06F9/4825
Abstract: In an embodiment of the invention, a method comprises: collecting a plurality of interrupts and servicing coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired. In another embodiment of the invention, an apparatus comprises: an interrupt controller configured to collect a plurality of interrupts and configured to service coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired. In yet another embodiment of the invention, an article of manufacture comprises: a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: collecting a plurality of interrupts and servicing coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired.
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Patent Agency Ranking
16.发明授权公开(公告)号：US09952991B1
公开(公告)日：2018-04-24
申请号：US14690339
申请日：2015-04-17
Applicant: BiTMICRO Networks, Inc.
Inventor： Ricardo H. Bruce , Marlon B. Verdan , Rowenah Michelle Jago-on
IPC: G06F5/12 , G06F13/28 , G06F13/40 , H04L12/801 , G06F5/14
CPC classification number: G06F13/28 , G06F5/12 , G06F5/14 , G06F13/4068 , H04L47/10
Abstract: In an embodiment of the invention, a method comprises: fetching a first set of descriptors from a memory device and writing the first set of descriptors to a buffer; retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access (DMA) operation; and if space is available in the buffer, fetching a second set of descriptors from the memory device and writing the second set of descriptors to the buffer during or after the processing of the first set of descriptors. In another embodiment of the invention, an apparatus comprises: a fetching module configured to fetch a first set of descriptors from a memory device and to write the first set of descriptors to a buffer; a sequencer configured to retrieve the first set of descriptors from the buffer and to process the first set of descriptors to permit a Direct Memory Access (DMA) operation; and wherein if space is available in the buffer, the fetching module is configured to fetch a second set of descriptors from the memory device and to write the second set of descriptors to the buffer during or after the processing of the first set of descriptors.
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公开(公告)号：US09875205B1
公开(公告)日：2018-01-23
申请号：US14217161
申请日：2014-03-17
Applicant: BiTMICRO Networks, Inc.
Inventor： Ricardo H. Bruce , Jarmie De La Cruz Espuerta , Marlon Basa Verdan
CPC classification number: G06F13/4031 , G06F13/385 , G06F13/4027
Abstract: A large network of memory system is described comprising a plurality of system controllers and flash memory modules, in accordance with an embodiment of the invention. An apparatus is also described comprising a plurality of flash memory modules interconnected with other flash memory modules and to at least one system controller via a point-to-point communication bus topology, in accordance with another embodiment of the invention.
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公开(公告)号：US09672178B1
公开(公告)日：2017-06-06
申请号：US14687700
申请日：2015-04-15
Applicant: BiTMICRO Networks, Inc.
Inventor： Cyrill C. Ponce , Marizonne O. Fuentes , Gianico G. Noble
CPC classification number: G06F13/37 , G06F3/061 , G06F3/0656 , G06F3/0683 , G06F13/28 , G06F13/287
Abstract: In an embodiment of the invention, a method comprises: A method, comprising: issuing, by a Direct Memory Access (DMA) engine, an update request to a dependency table if the DMA engine has finished executing a first descriptor; and issuing, by the DMA engine, a monitoring request if the DMA engine is executing a second descriptor that depends on a completion of a data transfer so that the DMA engine can monitor a status of a selected subindex related to the data transfer, wherein the subindex is in the dependency table. In another embodiment of the invention, an apparatus comprises: a Direct Memory Access (DMA) engine configured to issue an update request to a dependency table if the DMA engine has finished executing a first descriptor, and configured to issue a monitoring request if the DMA engine is executing a second descriptor that depends on a completion of a data transfer so that the DMA engine can monitor a status of a selected subindex related to the data transfer, wherein the subindex is in the dependency table.
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公开(公告)号：US08788725B2
公开(公告)日：2014-07-22
申请号：US13890229
申请日：2013-05-08
Applicant: BiTMICRO Networks, Inc.
IPC: G06F13/28
CPC classification number: G06F13/1657 , G06F12/00 , G06F12/0246 , G06F13/1673 , G06F13/1684 , G06F13/36
Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.
Abstract translation: 本发明涉及用于在至少一个DMA控制器与至少一个固态半导体存储器件（诸如NAND闪存器件等）之间传送信息的多电平存储器总线系统。 该多电平存储器总线系统包括耦合到中间总线的至少一个DMA控制器; 闪存总线; 以及中间总线和闪存总线之间的闪存缓冲电路。 该多级存储器总线系统可以被设置为支持：n位宽的总线宽度，例如半字节宽度或字节宽度的总线宽度; 中间总线上的可选择的数据采样率，例如单次或双次采样率; 可配置的总线数据速率，例如单，双，四进制或八进制数据采样率; CRC保护; 独家繁忙的机制; 专线忙 或这些的任何组合。
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公开(公告)号：US10055150B1
公开(公告)日：2018-08-21
申请号：US15170768
申请日：2016-06-01
Applicant: BiTMICRO Networks, Inc.
IPC: G06F3/06 , G06F12/0804 , G06F12/121
CPC classification number: G06F12/121 , G06F12/0804 , G06F12/0868 , G06F2212/1041 , G06F2212/222
Abstract: In an embodiment of the invention, a method comprises: requesting an update on a control data in at least one flash block in a storage memory; replicating, from the storage memory to a cache memory, the control data to be updated; moving a clean cache link list to a dirty cache link list so that the dirty cache link list is changed to reflect the update on the control data; and moving the dirty cache link list to a for-flush link list and writing an updated control data from the for-flush link list to a free flash page in the storage memory. In another embodiment of the invention, an apparatus comprises: a control data flushing system configured to: request an update on a control data in at least one flash block in a storage memory; replicate, from the storage memory to a cache memory, the control data to be updated; move a clean cache link list to a dirty cache link list so that the dirty cache link list is changed to reflect the update on the control data; and move the dirty cache link list to a for-flush link list and write an updated control data from the for-flush link list to a free flash page in the storage memory. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions operable to permit an apparatus to: request an update on a control data in at least one flash block in a storage memory; replicate, from the storage memory to a cache memory, the control data to be updated; move a clean cache link list to a dirty cache link list so that the dirty cache link list is changed to reflect the update on the control data; and move the dirty cache link list to a for-flush link list and write an updated control data from the for-flush link list to a free flash page in the storage memory.
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