公开(公告)号：US20050092598A1

公开(公告)日：2005-05-05

申请号：US10702970

申请日：2003-11-05

Applicant: Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

Inventor： Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

IPC: C23C14/16 ,  H01L21/285 ,  C23C16/00 ,  C23C14/32

CPC classification number: H01L21/28518 ,  C23C14/16

Abstract: A process for reducing the thermal budget and enhancing stability in the thermal budget of a metal salicide process used in the formation of metal salicides on substrates, thus eliminating or reducing salicide spiking and junction leakage in microelectronic devices fabricated on the substrates. According to a typical embodiment, a substrate is cooled to a sub-processing temperature which is lower than the metal deposition processing temperature and the salicide-forming metal is deposited onto the reduced-temperature substrate.

Abstract translation: 一种用于降低热预算并增强用于在基材上形成金属硅化物的金属硅化物工艺的热预算中的稳定性的方法，从而消除或减少在衬底上制造的微电子器件中的自杀剂尖峰和结漏电。 根据典型的实施方式，将基板冷却至比金属沉积处理温度低的副处理温度，并将形成自杀型化合物的金属沉积在还原温度基板上。

公开(公告)号：USD459150S1

公开(公告)日：2002-06-25

申请号：US29144669

申请日：2001-07-10

Applicant: Cheng Tung Lin

Designer： Cheng Tung Lin

公开(公告)号：US6042999A

公开(公告)日：2000-03-28

申请号：US73952

申请日：1998-05-07

Applicant: Cheng-Tung Lin ,  Yu-Hua Lee ,  Jenn Ming Huang ,  Cheng-Ming Wu

Inventor： Cheng-Tung Lin ,  Yu-Hua Lee ,  Jenn Ming Huang ,  Cheng-Ming Wu

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/768 ,  G03F7/26

CPC classification number: H01L21/76808 ,  G03F7/0035 ,  H01L21/0276

Abstract: A robust dual damascene process is disclosed where the substructure in a substrate is protected from damage caused by multiple etchings required in a damascene process by filling a contact or via hole opening with a protective material prior to the forming of the conductive line opening of the damascene structure having an etch-stop layer separating a lower and an upper dielectric layer. In the first embodiment, the protective material is partially removed from the hole opening reaching the substructure prior to the forming of the upper conductive line opening by etching. In the second embodiment, the protective material in the hole is removed at the same time the upper conductive line opening is formed by etching. In a third embodiment, the disclosed process is applied without the need of an etch-stop layer for the dual damascene process of this invention.

Abstract translation: 公开了一种稳健的双镶嵌工艺，其中通过在形成镶嵌导电线开口之前通过填充具有保护材料的接触或通孔开口来保护衬底中的子结构免受由镶嵌工艺中所需的多次蚀刻所造成的损伤 具有分隔下电介质层和上电介质层的蚀刻停止层的结构。 在第一实施例中，在通过蚀刻形成上导电线开口之前，保护材料部分地从到达底层结构的开孔中去除。 在第二实施例中，在通过蚀刻形成上导电线开口的同时去除孔中的保护材料。 在第三个实施例中，应用所公开的工艺，而不需要用于本发明的双镶嵌工艺的蚀刻停止层。

公开(公告)号：US5624867A

公开(公告)日：1997-04-29

申请号：US448670

申请日：1995-05-24

Applicant: Huang-Chung Cheng ,  Cheng-Tung Lin ,  Pei-Fen Chou

Inventor： Huang-Chung Cheng ,  Cheng-Tung Lin ,  Pei-Fen Chou

IPC: H01L21/225 ,  H01L21/283

CPC classification number: H01L21/28518 ,  H01L21/2257

Abstract: A low temperature process for forming palladium silicided shallow junctions in which ions are implanted into a palladium or a palladium silicide layer over a silicon substrate. The impurities are driven into the silicon substrate during the formation or recrystallization of the palladium silicide layer, and a diffusion region with shallow junction is formed in the substrate.

Abstract translation: 用于形成钯硅化物浅结的低温工艺，其中将离子注入到硅衬底上的钯或钯硅化物层中。 在硅化钯层的形成或重结晶过程中，杂质被驱入硅衬底，并且在衬底中形成具有浅结的扩散区。

公开(公告)号：USD368412S

公开(公告)日：1996-04-02

申请号：US36856

申请日：1995-03-29

Applicant: Cheng-Tung Lin

Designer： Cheng-Tung Lin

公开(公告)号：US08198685B2

公开(公告)日：2012-06-12

申请号：US12343307

申请日：2008-12-23

Applicant: Chung-Shi Liu ,  Yung-Sheng Chiu ,  Cheng-Tung Lin ,  Chen-Hua Yu

Inventor： Chung-Shi Liu ,  Yung-Sheng Chiu ,  Cheng-Tung Lin ,  Chen-Hua Yu

IPC: H01L27/092 ,  H01L21/28

CPC classification number: H01L29/517 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513

Abstract: A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MCxOy) containing layer is formed over the at least one first gate dielectric layer, wherein the transition-metal (M) has an atomic percentage of about 40 at. % or more. A first gate is formed over the first transition-metal oxycarbide containing layer. At least one first doped region is formed within the substrate and adjacent to a sidewall of the first gate.

Abstract translation: 半导体器件包括在衬底上的至少一个第一栅极电介质层。 在所述至少一个第一栅极介电层上形成含有第一过渡金属碳氧化物（MCxOy）的层，其中所述过渡金属（M）的原子百分比为约40原子。 ％ 或者更多。 在第一过渡金属含碳氧化物层上形成第一栅极。 至少一个第一掺杂区域形成在衬底内并且邻近第一栅极的侧壁。

公开(公告)号：US20110178171A1

公开(公告)日：2011-07-21

申请号：US13008597

申请日：2011-01-18

Applicant: Yi-Lin CHEN ,  Horng-Jyh Harn ,  Shinn-Zong Lin ,  Tzyy-Wen Chiou ,  Cheng-Tung Lin

Inventor： Yi-Lin CHEN ,  Horng-Jyh Harn ,  Shinn-Zong Lin ,  Tzyy-Wen Chiou ,  Cheng-Tung Lin

IPC: A61K31/365 ,  A61P35/00

CPC classification number: A61K31/365

Abstract: A method of inhibiting the cellular proliferation of at least one selected from the group consisting of androgen dependent prostate cancer cells, androgen independent prostate cancer cells, oral cancer cells, liver cancer cells (hepatoma), and gastric cancer cells in a subject is provided, wherein the method comprises administrating to the subject an effective amount of an active component selected from the group consisting of Z form isochaihulactone (Z-K8) of the following formula (I), E form isochaihulactone (E-K8) of the following formula (II), a pharmaceutically acceptable salt of Z-K8 or E-K8, a pharmaceutically acceptable ester of Z-K8 or E-K8, and combinations thereof: and R is H, alkoxy, or aryl. Also provided is a method for manufacturing Z-K8 and E-K8.

Abstract translation: 提供一种抑制受试者中选自雄激素依赖性前列腺癌细胞，雄激素依赖性前列腺癌细胞，口腔癌细胞，肝癌细胞（肝癌）和胃癌细胞的至少一种的细胞增殖的方法， 其中所述方法包括向受试者施用有效量的选自下式（I）的Z型异黄酮（Z-K8），下式的E型异黄酮（E-K8）（ II），Z-K8或E-K8的药学上可接受的盐，Z-K8或E-K8的药学上可接受的酯及其组合：R为H，烷氧基或芳基。 还提供了制造Z-K8和E-K8的方法。

公开(公告)号：US20100221878A1

公开(公告)日：2010-09-02

申请号：US12777937

申请日：2010-05-11

Applicant: Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

Inventor： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

IPC: H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.

Abstract translation: 公开了一种用于混合金属全硅化（FUSI）栅极结构的半导体器件和系统。 所述半导体系统包括PMOS栅极结构，所述PMOS栅极结构包括第一高<！ - SIPO < 介电层，P金属层，中间间隙金属层，其中中间间隙金属层形成在高金属层之间。 电介质层，P金属层和形成在P金属层上的完全硅化物层。 所述半导体系统还包括NMOS栅极结构，所述NMOS栅极结构包括第二高<！ - SIPO < 电介质层，完全硅化物层和中间间隙金属层，其中中间间隙金属层形成在高介电层之间。 电介质和完全硅化物层。

公开(公告)号：US20100155849A1

公开(公告)日：2010-06-24

申请号：US12343307

申请日：2008-12-23

Applicant: Chung-Shi LIU ,  Yung-Sheng Chiu ,  Cheng-Tung Lin ,  Chen-Hua Yu

Inventor： Chung-Shi LIU ,  Yung-Sheng Chiu ,  Cheng-Tung Lin ,  Chen-Hua Yu

IPC: H01L27/092 ,  H01L21/28

CPC classification number: H01L29/517 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513

Abstract: A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MCxOy) containing layer is formed over the at least one first gate dielectric layer, wherein the transition-metal (M) has an atomic percentage of about 40 at. % or more. A first gate is formed over the first transition-metal oxycarbide containing layer. At least one first doped region is formed within the substrate and adjacent to a sidewall of the first gate.

Abstract translation: 半导体器件包括在衬底上的至少一个第一栅极电介质层。 在所述至少一个第一栅极介电层上形成含有第一过渡金属碳氧化物（MCxOy）的层，其中所述过渡金属（M）的原子百分比为约40原子。 ％ 或者更多。 在第一过渡金属含碳氧化物层上形成第一栅极。 至少一个第一掺杂区域形成在衬底内并且邻近第一栅极的侧壁。

公开(公告)号：US20100151639A1

公开(公告)日：2010-06-17

申请号：US12712518

申请日：2010-02-25

Applicant: Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Jei Wang ,  CP Lo ,  Chih-Wei Chang

Inventor： Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Jei Wang ,  CP Lo ,  Chih-Wei Chang

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L29/665 ,  H01L21/76243 ,  H01L29/785

Abstract: Provided is a method of fabrication a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, the gate structure including a gate dielectric and a gate electrode disposed over the gate dielectric, forming source/drain regions in the semiconductor substrate at either side of the gate structure, forming a metal layer over the semiconductor substrate and the gate structure, the metal layer including a refractory metal layer or a refractory metal compound layer; forming an alloy layer over the metal layer; and performing an annealing thereby forming metal alloy silicides over the gate structure and the source/drain regions, respectively.

Abstract translation: 提供一种制造半导体器件的方法，其包括提供半导体衬底，在衬底上形成栅极结构，栅极结构包括栅极电介质和设置在栅极电介质上的栅电极，在半导体衬底中形成源极/漏极区域 在栅极结构的任一侧，在半导体衬底和栅极结构之上形成金属层，金属层包括难熔金属层或难熔金属化合物层; 在所述金属层上形成合金层; 并进行退火，从而分别在栅极结构和源极/漏极区域上形成金属合金硅化物。