公开(公告)号：US08797391B2

公开(公告)日：2014-08-05

申请号：US13007283

申请日：2011-01-14

Applicant: Chi-Chia Lin

Inventor： Chi-Chia Lin

IPC: H04N13/02 ,  H04N13/00 ,  H04N13/04

CPC classification number: H04N13/337 ,  H04N13/122 ,  H04N13/339

Abstract: A stereo image displaying method adapted to a polarizing panel is provided. The stereo image displaying method includes the following steps. An original first eye image and the original second eye image are received. Each of the odd pixel data rows of the original first eye image is interpolation operated with at least one of two adjacent even pixel data rows of original the first eye image to serve as one of a plurality of pixel data rows of a first eye image of a display frame. Each of the even pixel data rows of the original second eye image is interpolation operated with at least one of two adjacent odd pixel data rows of the original second eye image to serve as one of a plurality of pixel data rows of a second eye image of the display frame. The display frame is applied on the polarizing panel.

Abstract translation: 提供了一种适用于偏振面板的立体图像显示方法。 立体图像显示方法包括以下步骤。 接收原始第一眼睛图像和原始第二眼睛图像。 原始第一眼睛图像的奇数像素数据行中的每一个都是用第一眼睛图像的原始的两个相邻偶数像素数据行中的至少一个进行内插操作，以用作第一眼睛图像的第一眼睛图像的多个像素数据行中的一个 一个显示框架。 原始第二眼睛图像的每个偶数像素数据行是用原始第二眼睛图像的两个相邻的奇数像素数据行中的至少一个进行内插操作，以用作第二眼睛图像的第二眼睛图像的多个像素数据行中的一个 显示框架。 显示框架应用在偏光面板上。

公开(公告)号：US08772928B2

公开(公告)日：2014-07-08

申请号：US13205648

申请日：2011-08-09

Applicant: Chih-Ching Lin ,  Ya-Ting Chang ,  Chia-Lin Chuang

Inventor： Chih-Ching Lin ,  Ya-Ting Chang ,  Chia-Lin Chuang

IPC: H01L23/48

CPC classification number: H01L23/5286 ,  H01L23/5223 ,  H01L24/05

Abstract: An integrated circuit chip includes a power/ground interconnection network in a topmost metal layer over a semiconductor substrate and at least a bump pad on/over the power/ground interconnection network. The power/ground mesh interconnection network includes a first power/ground line connected to the bump pad and extending along a first direction, and a connection portion connected to the bump pad and extending along a second direction.

Abstract translation: 集成电路芯片包括位于半导体衬底上的最顶层金属层中的电源/接地互连网络，以及至少在电力/接地互连网络上/之上的凸块焊盘。 电源/接地网状互连网络包括连接到凸块焊盘并沿着第一方向延伸的第一电源/接地线，以及连接到凸块焊盘并沿第二方向延伸的连接部分。

公开(公告)号：US08716723B2

公开(公告)日：2014-05-06

申请号：US12270309

申请日：2008-11-13

Applicant: Ding-Yuan Chen ,  Chia-Lin Yu ,  Chen-Hua Yu ,  Wen-Chih Chiou

Inventor： Ding-Yuan Chen ,  Chia-Lin Yu ,  Chen-Hua Yu ,  Wen-Chih Chiou

IPC: H01L29/18

CPC classification number: H01L33/62 ,  H01L27/15 ,  H01L27/156 ,  H01L33/06 ,  H01L33/08 ,  H01L33/30 ,  H01L33/32 ,  H01L33/42 ,  H01L33/60

Abstract: A system and method for manufacturing a light-generating device is described. A preferred embodiment comprises a plurality of LEDs formed on a substrate. Each LED preferably has spacers along the sidewalls of the LED, and a reflective surface is formed on the substrate between the LEDs. The reflective surface is preferably located lower than the active layer of the individual LEDs.

Abstract translation: 描述了用于制造发光装置的系统和方法。 优选实施例包括形成在基板上的多个LED。 每个LED优选地具有沿LED的侧壁的间隔物，并且在LED之间的基板上形成反射表面。 反射表面优选地位于比各个LED的有源层更低的位置。

公开(公告)号：US08687393B2

公开(公告)日：2014-04-01

申请号：US13421851

申请日：2012-03-15

Applicant: Shu-Chia Lin ,  Wen-Yueh Hsieh ,  Ching-Yuan Lin

Inventor： Shu-Chia Lin ,  Wen-Yueh Hsieh ,  Ching-Yuan Lin

IPC: H02M3/24

CPC classification number: H02M7/53871 ,  H02M2001/0022

Abstract: A power converter module is disclosed, which is an all-digital module. The power converter module includes a reference voltage generation unit, a voltage loop control unit, a current loop control unit, an input voltage compensation unit, and a pulse width modulation generation unit, to transfer input power to stable output power for providing power to an external loading device through driving bridge switch unit with external driver. The voltage loop control unit and the current loop control unit contain a proportion-integral-differentiation controller for receiving signal related to voltage and current of loading device to form voltage control loop and current control loop. The pulse width modulation generation unit contains function of deciding necessary stop time to improve quality of output power and decrease the effect of input power and loading variation, and to provide stable sine-waveform output power to the external loading device.

Abstract translation: 公开了一种功率转换器模块，其是全数字模块。 功率转换器模块包括参考电压产生单元，电压环路控制单元，电流环路控制单元，输入电压补偿单元和脉冲宽度调制生成单元，用于将输入功率传送到稳定的输出功率，以向 外部负载装置通过驱动桥式开关单元与外部驱动器。 电压环控制单元和电流环控制单元包含一个比例积分微分控制器，用于接收与负载装置的电压和电流相关的信号，形成电压控制回路和电流控制回路。 脉冲宽度调制生成单元包含决定必要的停止时间以提高输出功率的质量并降低输入功率和负载变化的影响的功能，并向外部负载装置提供稳定的正弦波输出功率。

公开(公告)号：US20140065775A1

公开(公告)日：2014-03-06

申请号：US13603425

申请日：2012-09-05

Applicant: Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

IPC: H01L21/336

CPC classification number: H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon. The gate semiconductor layer covers a portion of the fin structure. Then a sacrificial layer is deposited to cover the fin structure entirely. Subsequently, a top surface of the fin structure is exposed from the sacrificial layer through an etching process. A material layer is then deposited, which covers the gate semiconductor layer, the fin structure and the sacrificial layer conformally. Finally, the material layer is etched until the top surface of the fin structure is exposed and a first spacer is concurrently formed on side surfaces of the gate semiconductor layer.

Abstract translation: 制造半导体器件的方法包括以下步骤。 首先，提供至少包括翅片结构和至少设置在其上的栅极半导体层的半导体衬底。 栅极半导体层覆盖翅片结构的一部分。 然后沉积牺牲层以完全覆盖翅片结构。 随后，翅片结构的顶表面通过蚀刻工艺从牺牲层露出。 然后沉积材料层，其共形地覆盖栅极半导体层，鳍结构和牺牲层。 最后，蚀刻材料层直到翅片结构的顶表面露出，并且在栅极半导体层的侧表面上同时形成第一间隔物。

公开(公告)号：USD700616S1

公开(公告)日：2014-03-04

申请号：US29422005

申请日：2012-05-15

Applicant: Chia-Lin Chao

Designer： Chia-Lin Chao

公开(公告)号：US08664928B2

公开(公告)日：2014-03-04

申请号：US13421847

申请日：2012-03-15

Applicant: Shu-Chia Lin ,  Wen-Yueh Hsieh ,  Ching-Yuan Lin

Inventor： Shu-Chia Lin ,  Wen-Yueh Hsieh ,  Ching-Yuan Lin

IPC: G05F1/00

CPC classification number: H02M3/158 ,  H02M1/4208 ,  H02M2001/009 ,  Y02B70/126 ,  Y10T307/258

Abstract: A digital power factor correction device is provided, which is an all-digital control module. The digital power factor correction device includes a voltage loop control unit, an input power control unit, a current loop control unit, and a pulse width modulation generation unit, to perform power factor correction for minimizing the phase difference between input current and input voltage through adjusting input current with an external driver and a switch unit. The voltage loop control unit and the current loop control unit contain a proportion-integral-differentiation controller to form a voltage control loop and a current control loop, respectively. The input power control unit adjusts current waveform according to the input power, while the pulse width modulation generation unit determines the stop time of pulse width modulation to produce a pulse width modulation signal, to control the external driver and the switch unit for eliminating loading effect.

Abstract translation: 提供了一种数字功率因数校正装置，它是全数字控制模块。 数字功率因数校正装置包括电压环路控制单元，输入功率控制单元，电流环路控制单元和脉冲宽度调制生成单元，以执行功率因数校正，以使输入电流和输入电压之间的相位差最小化 用外部驱动器和开关单元调节输入电流。 电压回路控制单元和电流回路控制单元分别包含比例积分微分控制器，分别形成电压控制回路和电流控制回路。 输入功率控制单元根据输入功率调整电流波形，而脉宽调制生成单元确定脉冲宽度调制的停止时间以产生脉宽调制信号，控制外部驱动器和开关单元以消除负载效应 。

公开(公告)号：US08659033B2

公开(公告)日：2014-02-25

申请号：US13267701

申请日：2011-10-06

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu ,  Hung-Ta Lin

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu ,  Hung-Ta Lin

IPC: H01L27/15 ,  H01L29/26 ,  H01L31/12 ,  H01L33/00

CPC classification number: H01L33/22 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/24 ,  H01L33/32

Abstract: A light-emitting diode (LED) device is provided. The LED device has raised semiconductor regions formed on a substrate. LED structures are formed over the raised semiconductor regions such that bottom contact layers and active layers of the LED device are conformal layers. The top contact layer has a planar surface. In an embodiment, the top contact layers are continuous over a plurality of the raised semiconductor regions while the bottom contact layers and the active layers are discontinuous between adjacent raised semiconductor regions.

Abstract translation: 提供了一种发光二极管（LED）装置。 LED装置已经凸起形成在基板上的半导体区域。 在凸起的半导体区域上形成LED结构，使得LED器件的底部接触层和有源层是保形层。 顶部接触层具有平坦的表面。 在一个实施例中，顶部接触层在多个凸起的半导体区域上是连续的，而底部接触层和有源层在相邻凸起的半导体区域之间是不连续的。

公开(公告)号：US20140035097A1

公开(公告)日：2014-02-06

申请号：US13564702

申请日：2012-08-01

Applicant: I-Chia Lin ,  Sheng-Jian Jou ,  Han-Chee Yen

Inventor： I-Chia Lin ,  Sheng-Jian Jou ,  Han-Chee Yen

IPC: H01L29/86 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3135 ,  H01L23/66 ,  H01L24/16 ,  H01L24/48 ,  H01L24/97 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01Q21/0087 ,  H01Q21/064 ,  H01Q21/065 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first substrate, a second substrate, an interposer substrate, a semiconductor chip, a package body and a first antenna layer. The first substrate comprises a grounding segment. The interposer substrate is disposed between the second substrate and the first substrate. The semiconductor chip is disposed on the second substrate. The package body encapsulates the second substrate, the semiconductor chip and the interposer substrate, and has a lateral surface and an upper surface. The first antenna layer is formed on the lateral surface and the upper surface of the package body, and electrically connected to the grounding segment.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括第一衬底，第二衬底，插入器衬底，半导体芯片，封装体和第一天线层。 第一基板包括接地段。 插入器基板设置在第二基板和第一基板之间。 半导体芯片设置在第二基板上。 封装体封装第二衬底，半导体芯片和插入器衬底，并且具有侧表面和上表面。 第一天线层形成在封装主体的侧表面和上表面上，并且电连接到接地段。

公开(公告)号：US20130307128A1

公开(公告)日：2013-11-21

申请号：US13472131

申请日：2012-05-15

Applicant: I-Chia Lin ,  Yu-Chou Tseng ,  Jin-Feng Yang ,  Chi-Sheng Chung ,  Kuo-Hsien Liao

Inventor： I-Chia Lin ,  Yu-Chou Tseng ,  Jin-Feng Yang ,  Chi-Sheng Chung ,  Kuo-Hsien Liao

IPC: H01L23/552 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L23/4334 ,  H01L23/49805 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Semiconductor packages and related methods. The semiconductor package includes a substrate, a semiconductor chip, a package body, a recess and a conductive layer. The substrate includes a grounding element. The semiconductor chip is disposed on the substrate and has a lateral surface and an upper surface. The package body encapsulates the lateral surface of the semiconductor chip. The recess is formed in the package body and exposes the upper surface of the semiconductor chip. The conductive layer covers an outer surface of the package body, the grounding element and the upper surface of the semiconductor chip exposed by the recess to provide both thermal dissipation and EMI shielding for the semiconductor chip.

Abstract translation: 半导体封装及相关方法。 半导体封装包括衬底，半导体芯片，封装体，凹部和导电层。 基板包括接地元件。 半导体芯片设置在基板上并且具有侧表面和上表面。 封装体封装半导体芯片的侧表面。 凹部形成在封装主体中，并露出半导体芯片的上表面。 导电层覆盖封装主体的外表面，接地元件和由凹部暴露的半导体芯片的上表面，以为半导体芯片提供散热和EMI屏蔽。