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    Analog Circuits Incorporating Magnetic Logic Units
    12.
    发明申请
    Analog Circuits Incorporating Magnetic Logic Units 有权
    包含磁性逻辑单元的模拟电路

    公开(公告)号：US20150214953A1

    公开(公告)日：2015-07-30

    申请号：US14606967

    申请日：2015-01-27

    Applicant: Crocus Technology Inc.

    Inventor： Douglas J. Lee ,  Yaron Oren-Pines ,  Stuart Desmond Rumley ,  Seyed A. Tabatabaei ,  Bertrand F. Cambou

    IPC: H03K19/18

    CPC classification number: H03K19/18 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L21/822 ,  H03B15/006 ,  H03D7/00 ,  H03D2200/0074

    Abstract: A circuit includes a magnetic logic unit including input terminals, output terminals, a field line, and magnetic tunnel junctions (MTJs). The field line electrically connects a first and a second input terminal, and is configured to generate a magnetic field based on an input to at least one of the first and the second input terminal. The input is based on a first analog input to the circuit. Each MTJ is electrically connected to a first and a second output terminal, and is configured such that an output of at least one of the first and the second output terminal varies in response to a combined resistance of the MTJs. The resistance of the MTJs varies based on the magnetic field. The circuit is configured to mix the first analog input and a second analog input to generate an analog output based on the output of the second output terminal.

    Abstract translation: 电路包括包括输入端子，输出端子，场线和磁隧道结（MTJ）的磁逻辑单元。 场线电连接第一和第二输入端子，并且被配置为基于对第一和第二输入端子中的至少一个的输入产生磁场。 输入基于电路的第一个模拟输入。 每个MTJ电连接到第一和第二输出端，并且被配置为使得第一和第二输出端中的至少一个的输出响应于MTJ的组合电阻而变化。 MTJ的电阻根据磁场而变化。 电路被配置为混合第一模拟输入和第二模拟输入以基于第二输出端的输出产生模拟输出。

    Magnetic logic units configured as an amplifier
    13.
    发明授权
    Magnetic logic units configured as an amplifier 有权
    配置为放大器的磁逻辑单元

    公开(公告)号：US08933750B2

    公开(公告)日：2015-01-13

    申请号：US13769156

    申请日：2013-02-15

    Applicant: Crocus Technology Inc.

    Inventor： Bertrand F. Cambou ,  Douglas J. Lee ,  Ken Mackay

    IPC: H03F15/00 ,  G11C11/02 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16

    CPC classification number: H03F15/00 ,  G11C11/02 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H03F19/00

    Abstract: An apparatus includes a circuit and a field line. The circuit includes a magnetic tunnel junction including a storage layer and a sense layer. The field line is configured to generate a magnetic field based on an input signal, where the magnetic tunnel junction is configured such that a magnetization direction of the sense layer and a resistance of the magnetic tunnel junction vary based on the magnetic field. The circuit is configured to amplify the input signal to generate an output signal that varies in response to the resistance of the magnetic tunnel junction.

    Abstract translation: 一种装置包括电路和场线。 该电路包括一个包括存储层和感应层的磁性隧道结。 场线被配置为基于输入信号产生磁场，其中磁性隧道结被配置为使得感测层的磁化方向和磁性隧道结的电阻基于磁场而变化。 电路被配置为放大输入信号以产生响应于磁性隧道结的电阻而变化的输出信号。

    Memory devices with magnetic random access memory (MRAM) cells and associated structures for connecting the MRAM cells
    14.
    发明授权
    Memory devices with magnetic random access memory (MRAM) cells and associated structures for connecting the MRAM cells 有权
    具有磁性随机存取存储器（MRAM）单元和用于连接MRAM单元的相关结构的存储器件

    公开(公告)号：US08816455B2

    公开(公告)日：2014-08-26

    申请号：US13657708

    申请日：2012-10-22

    Applicant: Crocus Technology, Inc.

    Inventor： Neal Berger ,  Mourad El Baraji ,  Amitay Levi

    IPC: H01L29/82

    CPC classification number: H01L27/222 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/82 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.

    Abstract translation: 存储器件包括包括多个磁随机存取存储器（MRAM）单元的磁性层，第一导电层，包括连接多个MRAM单元中包括的MRAM单元的带的层和第二导电层。 第一导电层包括电连接到多个MRAM单元中的至少一个的导电部分，以及被配置为将数据写入多个MRAM单元中的至少一个的场线。 第二导电层包括电连接到多个MRAM单元中的至少一个MRAM单元的导电互连，其中磁性层设置在第一导电层和第二导电层之间。 多个MRAM单元中的至少一个直接附接到第二导电层和带。

    Apparatus, System, and Method for Writing Multiple Magnetic Random Access Memory Cells with a Single Field Line
    16.
    发明申请
    Apparatus, System, and Method for Writing Multiple Magnetic Random Access Memory Cells with a Single Field Line 有权
    用单场线写入多个磁性随机存取存储单元的装置，系统和方法

    公开(公告)号：US20130094283A1

    公开(公告)日：2013-04-18

    申请号：US13648221

    申请日：2012-10-09

    Applicant: CROCUS TECHNOLOGY, INC.

    Inventor： Neal Berger ,  Jean-Pierre Nozieres ,  Virgile Javerliac

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C8/08 ,  G11C11/1659 ,  G11C11/1693

    Abstract: A memory device includes a plurality of magnetic random access memory (MRAM) cells, a field line, and a field line controller configured to generate a write sequence that traverses the field line. The write sequence is for writing a multi-bit word to the plurality of MRAM cells. The multi-bit word includes a first subset of bits having a first polarity and a second subset of bits having a second polarity. The write sequence writes concurrently to at least a subset of the plurality of MRAM cells corresponding to the first subset of bits having the first polarity, then subsequently writes concurrently to a remaining subset of the plurality of MRAM cells corresponding to the second subset of bits having the second polarity.

    Abstract translation: 一种存储器件包括多个磁性随机存取存储器（MRAM）单元，一个场线，以及一个现场线控制器，被配置为产生穿过场线的写入序列。 写入序列用于将多位字写入多个MRAM单元。 多位字包括具有第一极性的位的第一子集和具有第二极性的位的第二子集。 所述写入顺序并行地写入与具有所述第一极性的所述第一第一子集对应的所述多个MRAM单元的至少一个子集，然后并行地写入所述多个MRAM单元的对应于具有 第二极性。

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