公开(公告)号：US10282214B2

公开(公告)日：2019-05-07

申请号：US15333704

申请日：2016-10-25

Applicant: DOLPHIN INTEGRATION

Inventor： Olivier Monfort ,  Lionel Jure ,  Gauthier Reveret ,  Sébastien Genevey

IPC: G06F1/08 ,  G06F1/10 ,  G06F1/32 ,  G06F9/445 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/3206

Abstract: The invention concerns a computing system comprising: a plurality of islands capable of operating in one of a plurality of operating modes, a first island being coupled to a first island control circuit and a second island being coupled to a second island control circuit; a first mediation circuit coupled to the first and second island control circuits and adapted: to receive a first request from the first island control circuit to change a current operating mode of the first island; to receive a second request from the second island control circuit to change a current operating mode of the second island; and to control a first voltage supply circuit and/or a first clock generator to change a voltage and/or clock signal supplied to the first and second islands based on the first and second requests.

公开(公告)号：US20180197585A1

公开(公告)日：2018-07-12

申请号：US15866156

申请日：2018-01-09

Applicant: Dolphin Integration

Inventor： Julien Louche ,  Olivier Mercier ,  Khaja Ahmad Shaik

IPC: G11C7/12 ,  G11C5/14 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C7/10 ,  G11C7/18 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/418 ,  G11C11/419

Abstract: A memory circuit having: a control circuit of a line of a memory array including: a first transistor coupled between first and second nodes and controlled by a line selection signal including a high level and a low level; a second transistor controlled by a first signal and coupled between the first node and a voltage supply rail of a first supply voltage, the first supply voltage being higher than the high level of the line selection signal, the first node being coupled to a line of memory array, the second node receiving a timing signal; and a line deactivation circuit adapted to generate the first signal and including a reference cell and a level shifter.

公开(公告)号：US20170132021A1

公开(公告)日：2017-05-11

申请号：US15333704

申请日：2016-10-25

Applicant: DOLPHIN INTEGRATION

Inventor： Olivier MONFORT ,  Lionel JURE ,  Gauthier REVERET ,  Sébastien GENEVEY

IPC: G06F9/445 ,  G06F1/32 ,  G06F1/08

CPC classification number: G06F9/44505 ,  G06F1/08 ,  G06F1/10 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: The invention concerns a computing system comprising: a plurality of islands capable of operating in one of a plurality of operating modes, a first island being coupled to a first island control circuit and a second island being coupled to a second island control circuit; a first mediation circuit coupled to the first and second island control circuits and adapted: to receive a first request from the first island control circuit to change a current operating mode of the first island; to receive a second request from the second island control circuit to change a current operating mode of the second island; and to control a first voltage supply circuit and/or a first clock generator to change a voltage and/or clock signal supplied to the first and second islands based on the first and second requests.

公开(公告)号：US09564208B2

公开(公告)日：2017-02-07

申请号：US14871508

申请日：2015-09-30

Applicant: Dolphin Integration

Inventor： Oron Chertkow ,  Ariel Pescovsky

IPC: G11C14/00 ,  G11C11/412 ,  G11C16/04 ,  G11C16/10 ,  G11C5/00 ,  G11C29/00

CPC classification number: G11C11/4125 ,  G11C5/005 ,  G11C14/00 ,  G11C16/0441 ,  G11C16/10 ,  G11C29/789

Abstract: The invention concerns a memory cell having: first and second cross-coupled gated inverters (102, 104), each including first and second inputs (IN1, IN2) and an output (OUT) and being adapted to couple its output to a first logic level only when the first and second inputs both receive the inverse of the first logic level; a first cut-off circuit (106) coupling the second input (IN2) of the first gated inverter (102) to the first input (IN1) of the first gated inverter (102); and a second cut-off circuit (108) coupling the second input (IN2) of the second gated inverter (104) to the first input (IN1) of the second gated inverter (104).

Abstract translation: 本发明涉及一种存储器单元，其具有：第一和第二交叉耦合门控反相器（102,104），每个反相器包括第一和第二输入（IN1，IN2）和输出（OUT），并且适于将其输出耦合到第一逻辑 只有当第一和第二输入都接收到第一逻辑电平的反相时; 将第一选通逆变器（102）的第二输入（IN2）与第一选通逆变器（102）的第一输入（IN1）耦合的第一截止电路（106）; 以及将第二选通逆变器（104）的第二输入（IN2）与第二门控逆变器（104）的第一输入（IN1）耦合的第二截止电路（108）。

公开(公告)号：US09269423B2

公开(公告)日：2016-02-23

申请号：US14051357

申请日：2013-10-10

Applicant: DOLPHIN INTEGRATION

Inventor： Ilan Sever

IPC: G11C7/10 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C29/08 ,  G11C7/22

CPC classification number: G11C11/412 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/418 ,  G11C11/419 ,  G11C29/08

Abstract: The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.

Abstract translation: 本发明涉及具有以列和行排列的存储单元的存储器阵列，每列的存储单元耦合到其列的至少一个公共写入线，每行的存储单元耦合到其行的公共选择行 其中每个存储单元包括由在第一和第二存储节点之间交叉耦合的一对反相器形成的锁存器; 耦合在第一存储节点和第一测试数据输入之间的第一晶体管; 以及耦合在所述第二存储节点和第二测试数据输入之间的第二晶体管。