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    Semiconductor memory devices including offset active regions
    11.
    发明授权
    Semiconductor memory devices including offset active regions 有权
    包括偏移活动区域的半导体存储器件

    公开(公告)号：US07547936B2

    公开(公告)日：2009-06-16

    申请号：US11246594

    申请日：2005-10-06

    Applicant: Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    Inventor： Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    IPC: H01L271/108

    CPC classification number: H01L27/11502 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855

    Abstract: A semiconductor memory device may include a substrate having a plurality of active regions and a field isolation layer on the substrate surrounding the active regions of the substrate. Each of the plurality of active regions may have a length in a direction of a first axis and a width in a direction of a second axis, and the length may be greater than the width. The plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis, and active regions of adjacent columns may be offset in the direction of the second axis.

    Abstract translation: 半导体存储器件可以包括具有多个有源区的衬底和围绕衬底的有源区的衬底上的场隔离层。 多个有源区域中的每一个可以具有在第一轴线的方向上的长度和在第二轴线的方向上的宽度，并且该长度可以大于宽度。 多个有源区域可以沿着第二轴线的方向设置在多个活性区域列中，并且相邻列的有效区域可以在第二轴线的方向上偏移。

    DRAM devices having an increased density layout
    12.
    发明授权
    DRAM devices having an increased density layout 失效
    具有增加的密度布局的DRAM器件

    公开(公告)号：US07221014B2

    公开(公告)日：2007-05-22

    申请号：US11015993

    申请日：2004-12-17

    Applicant: Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

    Inventor： Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

    IPC: H01L29/74 ,  H01L29/76

    CPC classification number: H01L27/10888 ,  H01L27/0207 ,  H01L27/10814

    Abstract: DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2 in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.

    Abstract translation: DRAM装置包括沿第一方向延伸的多个字线和沿第二方向延伸并与字线相交的多个位线。 提供了多个有源区域，其被电耦合到字线和位线。 每个有源区域以最小线宽度F来限定具有6F 2的面积的单个单元存储单元。每个有源区域可以仅由一条字线重叠，并且有源区域 可以由隔离区限定。

    Method of forming self-aligned contact pads of non-straight type semiconductor memory device
    14.
    发明授权
    Method of forming self-aligned contact pads of non-straight type semiconductor memory device 有权
    形成非直型半导体存储器件的自对准接触焊盘的方法

    公开(公告)号：US07064051B2

    公开(公告)日：2006-06-20

    申请号：US10944151

    申请日：2004-09-16

    Applicant: Eun-Mi Lee ,  Doo-Hoon Goo ,  Jung-Hyeon Lee ,  Gi-Sung Yeo

    Inventor： Eun-Mi Lee ,  Doo-Hoon Goo ,  Jung-Hyeon Lee ,  Gi-Sung Yeo

    IPC: H01L21/3205 ,  H01L21/4763

    CPC classification number: H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the invention provide methods of forming SAC pads in non-straight semiconductor device having non-straight type or separate type active regions. A plurality of gate line structures extending in one direction may be formed on a semiconductor substrate having non-straight active regions. An interlayer insulating layer covering gate line structures may be formed on the gate line structures. Then, a photo-resist layer may be formed on the interlayer insulating layer. A photo-resist pattern may be formed through exposing and developing the photo-resist layer by using a photo-mask having, for example, a bar type, a wave type, or a reverse active type pattern. Then, contact holes exposing source/drain regions may be formed by etching the interlayer insulating layer using the photo-resist pattern as an etching mask. Contact pads may then be formed by filling the contact holes with a conductive material.

    Abstract translation: 本发明的实施例提供了在具有非直型或分离型有源区的非直线半导体器件中形成SAC焊盘的方法。 可以在具有非直线活性区域的半导体衬底上形成沿一个方向延伸的多个栅极线结构。 覆盖栅极线结构的层间绝缘层可以形成在栅极线结构上。 然后，可以在层间绝缘层上形成光致抗蚀剂层。 可以通过使用具有例如条形，波型或反向活性型图案的光掩模，通过曝光和显影光致抗蚀剂层来形成光刻胶图案。 然后，可以通过使用光刻胶图案作为蚀刻掩模蚀刻层间绝缘层来形成暴露源极/漏极区的接触孔。 然后可以通过用导电材料填充接触孔来形成接触垫。

    Apparatus and method for forming a film on a tape substrate
    15.
    发明授权
    Apparatus and method for forming a film on a tape substrate 有权
    用于在带基材上形成膜的装置和方法

    公开(公告)号：US6147033A

    公开(公告)日：2000-11-14

    申请号：US407892

    申请日：1999-09-29

    Applicant: Do Jun Youm ,  Doo Hoon Goo ,  Sang Hyun Oh

    Inventor： Do Jun Youm ,  Doo Hoon Goo ,  Sang Hyun Oh

    IPC: C23C14/56 ,  C23C16/54 ,  H01B13/00 ,  H01L39/24 ,  C23C14/00

    CPC classification number: C23C14/562 ,  C23C16/545 ,  H01L39/2432

    Abstract: This invention relates to an apparatus and method for forming a high temperature superconducting film on a tape substrate. In this invention, the superconducting film is deposited on the tape substrate wound around a cylindrical substrate holder inserted in an auxiliary chamber. The holder rotates during the whole deposition process. Vapors of film materials are supplied from a main chamber through an opening between the two chambers. According to the present invention, it is possible to form a highly uniform high temperature superconducting film on a tape substrate at high speeds suitable for large scale production. The manufacturing speed can easily be controlled by the size of the substrate holder.

    Abstract translation: 本发明涉及一种在带基材上形成高温超导膜的装置和方法。 在本发明中，超导膜沉积在卷绕在插入辅助室中的圆柱形基片架上的带基片上。 保持架在整个沉积过程中旋转。 薄膜材料的蒸气从主室通过两个室之间的开口供应。 根据本发明，可以在适于大规模生产的高速下在带基材上形成高度均匀的高温超导膜。 制造速度可以容易地通过基板支架的尺寸来控制。

    Method of forming trench in semiconductor device
    17.
    发明授权
    Method of forming trench in semiconductor device 失效
    在半导体器件中形成沟槽的方法

    公开(公告)号：US07259065B2

    公开(公告)日：2007-08-21

    申请号：US11080891

    申请日：2005-03-16

    Applicant: Doo-hoon Goo ,  Si-hyeung Lee ,  Han-ku Cho ,  Sang-gyun Woo ,  Gi-sung Yeo

    Inventor： Doo-hoon Goo ,  Si-hyeung Lee ,  Han-ku Cho ,  Sang-gyun Woo ,  Gi-sung Yeo

    IPC: H01L21/336

    CPC classification number: H01L27/10876 ,  H01L21/3083 ,  H01L27/0207

    Abstract: There are provided a method of forming a trench for a recessed channel of a transistor and a layout for the same. A layout for the recessed channel according to one aspect of the present invention is formed such that an open region is extended across at least one of a first active region in a lateral direction, and also across another second active region in parallel with the first active region in a diagonal direction, and the extension is cut not to reach an isolation region between two third active regions that are in parallel with the second active region in a diagonal direction, and have noses facing each other in a longitudinal direction, and the layout includes an alignment of a plurality of open regions, which are discontinuously aligned. An etch mask is formed using the layout, and a semiconductor substrate is etched using the etch mask, and a trench for a recessed channel is formed on the active region.

    Abstract translation: 提供了一种形成用于晶体管的凹槽的沟槽的方法及其布局。 根据本发明的一个方面的凹陷通道的布局被形成为使得开放区域跨越横向方向上的第一有源区域中的至少一个延伸，并且还跨越与第一活性物体平行的另一个第二有源区域 区域，并且延伸部被切割成不能在对角线方向上到达与第二有源区域平行的两个第三有源区域之间的隔离区域，并且在纵向方向上具有彼此面对的鼻子，并且布局 包括不连续对准的多个开放区域的对准。 使用布局形成蚀刻掩模，并且使用蚀刻掩模蚀刻半导体衬底，并且在有源区上形成用于凹陷沟道的沟槽。

    Dram devices having an increased density layout
    19.
    发明申请
    Dram devices having an increased density layout 失效
    具有增加密度布局的戏剧装置

    公开(公告)号：US20050269615A1

    公开(公告)日：2005-12-08

    申请号：US11015993

    申请日：2004-12-17

    Applicant: Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

    Inventor： Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

    IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/02 ,  H01L29/74

    CPC classification number: H01L27/10888 ,  H01L27/0207 ,  H01L27/10814

    Abstract: DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2 in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.

    Abstract translation: DRAM装置包括沿第一方向延伸的多个字线和沿第二方向延伸并与字线相交的多个位线。 提供了多个有源区域，其被电耦合到字线和位线。 每个有源区域以最小线宽度F来限定具有6F 2的面积的单个单元存储单元。每个有源区域可以仅由一条字线重叠，并且有源区域 可以由隔离区限定。

    Method of forming self-aligned contact pads of non-straight type semiconductor memory device
    20.
    发明申请
    Method of forming self-aligned contact pads of non-straight type semiconductor memory device 有权
    形成非直型半导体存储器件的自对准接触焊盘的方法

    公开(公告)号：US20050070080A1

    公开(公告)日：2005-03-31

    申请号：US10944151

    申请日：2004-09-16

    Applicant: Eun-Mi Lee ,  Doo-Hoon Goo ,  Jung-Hyeon Lee ,  Gi-Sung Yeo

    Inventor： Eun-Mi Lee ,  Doo-Hoon Goo ,  Jung-Hyeon Lee ,  Gi-Sung Yeo

    IPC: H01L21/28 ,  H01L21/4763 ,  H01L21/60 ,  H01L23/485

    CPC classification number: H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the invention provide methods of forming SAC pads in non-straight semiconductor device having non-straight type or separate type active regions. A plurality of gate line structures extending in one direction may be formed on a semiconductor substrate having non-straight active regions. An interlayer insulating layer covering gate line structures may be formed on the gate line structures. Then, a photo-resist layer may be formed on the interlayer insulating layer. A photo-resist pattern may be formed through exposing and developing the photo-resist layer by using a photo-mask having, for example, a bar type, a wave type, or a reverse active type pattern. Then, contact holes exposing source/drain regions may be formed by etching the interlayer insulating layer using the photo-resist pattern as an etching mask. Contact pads may then be formed by filling the contact holes with a conductive material.

    Abstract translation: 本发明的实施例提供了在具有非直型或分离型有源区的非直线半导体器件中形成SAC焊盘的方法。 可以在具有非直线活性区域的半导体衬底上形成沿一个方向延伸的多个栅极线结构。 覆盖栅极线结构的层间绝缘层可以形成在栅极线结构上。 然后，可以在层间绝缘层上形成光致抗蚀剂层。 可以通过使用具有例如棒型，波型或反向活性型图案的光掩模，通过曝光和显影光致抗蚀剂层来形成光致抗蚀剂图案。 然后，可以通过使用光刻胶图案作为蚀刻掩模蚀刻层间绝缘层来形成暴露源极/漏极区的接触孔。 然后可以通过用导电材料填充接触孔来形成接触垫。

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