公开(公告)号：US07382055B2

公开(公告)日：2008-06-03

申请号：US11846595

申请日：2007-08-29

Applicant: Eric M. Coker ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Matthew D. Moon ,  Anthony K. Stamper

Inventor： Eric M. Coker ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Matthew D. Moon ,  Anthony K. Stamper

IPC: H01L29/40

CPC classification number: H01L27/016

Abstract: A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.

Abstract translation: 适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。 第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。 同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

公开(公告)号：US20080122574A1

公开(公告)日：2008-05-29

申请号：US11458494

申请日：2006-07-19

Applicant: Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  John E. Florkey ,  Robert M. Rassel ,  Kunal Vaed

Inventor： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  John E. Florkey ,  Robert M. Rassel ,  Kunal Vaed

IPC: H01C1/06 ,  H01L21/20

CPC classification number: H01L27/0802 ,  H01L21/26513 ,  H01L28/20

Abstract: A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.

Abstract translation: 含多晶硅的电阻器包括：（1）选自硼和二氟化硼的p掺杂剂; 和（2）选自砷和磷的n掺杂剂。 p掺杂剂和n掺杂剂中的每一个掺杂剂的掺杂剂浓度从每立方厘米约1e18至约1e21掺杂剂原子。 用于形成多晶硅电阻器的方法使用相对于每平方厘米约1e14至约1e16掺杂剂离子的注入剂量。 p掺杂剂和n掺杂剂可以同时或顺序地提供。 对于具有约100至约5000欧姆/平方的薄层电阻的多晶硅电阻器，该方法提供某些多晶硅电阻器的薄层电阻百分比标准偏差小于约1.5％。

公开(公告)号：US07301752B2

公开(公告)日：2007-11-27

申请号：US10709907

申请日：2004-06-04

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Zhong-Xiang He ,  Matthew D. Moon ,  Vidhya Ramachandran ,  Barbara Waterhouse

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Zhong-Xiang He ,  Matthew D. Moon ,  Vidhya Ramachandran ,  Barbara Waterhouse

IPC: H01G4/38

CPC classification number: H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

Abstract translation: 公开了一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法。 在该方法中，在下导体层的上方形成电介质层，在电介质层的上方形成上导体层。 然后，本发明在上导体层和电介质层之上形成蚀刻停止层，并在蚀刻停止层上形成硬掩模（氧化硅硬掩模，氮化硅硬掩模等）。 接下来，在硬掩模上形成光致抗蚀剂，这允许通过光致抗蚀剂蚀刻硬掩模，蚀刻停止层，电介质层和下导体层。

公开(公告)号：US07285472B2

公开(公告)日：2007-10-23

申请号：US10905940

申请日：2005-01-27

Applicant: Douglas D. Coolbaugh ,  John E. Florkey ,  Robert M. Rassel

Inventor： Douglas D. Coolbaugh ,  John E. Florkey ,  Robert M. Rassel

IPC: H01L21/8222

CPC classification number: H01L21/26513 ,  H01L27/0802 ,  H01L28/20

Abstract: Various methods of fabricating a high precision, silicon-containing resistor in which the resistor is formed as a discrete device integrated in complementary metal oxide semiconductor (CMOS) processing utilizing low temperature silicidation are provided. In some embodiments, the Si-containing layer is implanted with a high dose of ions prior to activation. The activation can be performed by the deposition of a protective dielectric layer, or a separate activation anneal. In another embodiment, a highly doped in-situ Si-containing layer is used thus eliminating the need for implanting into the Si-containing layer.

Abstract translation: 提供制造高精度含硅电阻器的各种方法，其中电阻器形成为集成在利用低温硅化物的互补金属氧化物半导体（CMOS）处理中的分立器件）。 在一些实施方案中，在活化之前，用高剂量的离子注入含Si层。 激活可以通过沉积保护性介电层或单独的激活退火来进行。 在另一个实施方案中，使用高掺杂的原位含Si层，因此不需要植入含Si层。

公开(公告)号：US07129561B2

公开(公告)日：2006-10-31

申请号：US10707065

申请日：2003-11-19

Applicant: Douglas D. Coolbaugh ,  Daniel C. Edelstein ,  Robert A. Groves ,  Zhong-Xiang He

Inventor： Douglas D. Coolbaugh ,  Daniel C. Edelstein ,  Robert A. Groves ,  Zhong-Xiang He

IPC: H01L29/00 ,  H01F5/00

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high performance inductor which has a relatively low sheet resistance that can be integrated within a semiconductor interconnect structure and can be used in RF applications, including RF CMOS and SiGe technologies, is provided. The inductor is either a dual-metal inductor including a first layer of metal which serves as an upper metal wire in the semiconductor structure and a second layer of metal located directly on top of the first layer of metal, or a tri metal inductor, which includes a third layer of metal located directly on top of the second layer of metal. No vias are located between the various metal layers of the inventive inductor.

Abstract translation: 提供了具有相对低的薄层电阻的高性能电感器，其可以集成在半导体互连结构内并且可以用于RF应用中，包括RF CMOS和SiGe技术。 电感器是双金属电感器，其包括在半导体结构中用作上部金属线的第一金属层和位于第一金属层的顶部的第二金属层或三金属电感器，其中， 包括直接位于第二金属层顶部的第三层金属。 在本发明的电感器的各种金属层之间没有通孔。

公开(公告)号：US06878976B2

公开(公告)日：2005-04-12

申请号：US10063025

申请日：2002-03-13

Applicant: Douglas D. Coolbaugh ,  Steven H. Voldman

Inventor： Douglas D. Coolbaugh ,  Steven H. Voldman

IPC: H01L27/02 ,  H01L29/08 ,  H01L29/24 ,  H01L29/737 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L29/0821 ,  H01L27/0259 ,  H01L29/1608 ,  H01L29/7378

Abstract: Selectively implanting carbon in a transistor lowers the collector-to-emitter breakdown (BVCEO) of the transistor. This transistor, with the lowered BVCEO, is then used as a “trigger” device in an Electrostatic Discharge (ESD) power clamp comprising a first low breakdown trigger device and a second high breakdown clamp device. ESD power clamps are constructed using epitaxial base pseudomorphic Silicon Germanium heterojunction transistors in a common-collector Darlington configuration.

Abstract translation: 在晶体管中选择性地注入碳以降低晶体管的集电极到发射极击穿（BVCEO）。 具有降低的BVCEO的该晶体管然后用作包括第一低击穿触发器件和第二高击穿钳位装置的静电放电（ESD）功率钳中的“触发器”。 ESD功率钳位采用共同收集器达林顿配置中的外延基本伪晶体硅锗异质结晶体管构建。

公开(公告)号：US06803269B2

公开(公告)日：2004-10-12

申请号：US10064754

申请日：2002-08-14

Applicant: Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Mohamed Youssef Hammad ,  Jeffrey B. Johnson

Inventor： Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Mohamed Youssef Hammad ,  Jeffrey B. Johnson

IPC: H01L218238

CPC classification number: H01L29/93 ,  H01L27/0808 ,  Y10S438/979

Abstract: A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.

公开(公告)号：US06429101B1

公开(公告)日：2002-08-06

申请号：US09240753

申请日：1999-01-29

Applicant: Ricky S. Amos ,  Arne W. Ballantine ,  Gregory Bazan ,  Bomy A. Chen ,  Douglas D. Coolbaugh ,  Ramachandra Divakaruni ,  Heidi L. Greer ,  Herbert L. Ho ,  Joseph F. Kudlacik ,  Bernard P. Leroy ,  Paul C. Parries ,  Gary L. Patton

Inventor： Ricky S. Amos ,  Arne W. Ballantine ,  Gregory Bazan ,  Bomy A. Chen ,  Douglas D. Coolbaugh ,  Ramachandra Divakaruni ,  Heidi L. Greer ,  Herbert L. Ho ,  Joseph F. Kudlacik ,  Bernard P. Leroy ,  Paul C. Parries ,  Gary L. Patton

IPC: H01L2120

CPC classification number: H01L21/02126 ,  H01L21/0214 ,  H01L21/02236 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/31662

Abstract: A method for forming a thermally stable ohmic contact structure that includes a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of dielectric material is formed between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.

Abstract translation: 一种形成包含单晶半导体区域和多晶半导体区域的热稳定欧姆接触结构的方法。 在单晶半导体区域的至少一部分与多晶半导体区域之间形成介电材料的至少一个区域，从而控制多晶半导体的晶粒生长。

公开(公告)号：US06399458B1

公开(公告)日：2002-06-04

申请号：US09400676

申请日：1999-09-21

Applicant: Douglas D. Coolbaugh ,  David L. Harame

Inventor： Douglas D. Coolbaugh ,  David L. Harame

IPC: H01L2120

CPC classification number: H01L21/26513 ,  H01L21/02381 ,  H01L21/02667 ,  H01L21/2022

Abstract: A method of forming a diffusion region in a silicon substrate having low-resistance, acceptable defect density, reliability and process control comprising the steps of: (a) subjecting a silicon substrate to a first ion implantation step, said first ion implantation step being conducted under conditions such that a region of amorphized Si is formed in said silicon substrate; (b) subjecting said silicon substrate containing said region of amorphized Si to a second ion implantation step, said second ion implantation step being carried out by implanting a dopant ion into said silicon substrate under conditions such that the peak of implant of said dopant ion is within the region of amorphized Si; and (c) annealing said silicon substrate under conditions such that said region of amorphized Si is re-crystallized thereby forming a diffusion region in said silicon substrate is provided.

公开(公告)号：US08753950B2

公开(公告)日：2014-06-17

申请号：US13432421

申请日：2012-03-28

Applicant: Douglas D. Coolbaugh ,  Keith E. Downes ,  Peter J. Lindgren ,  Anthony K. Stamper

Inventor： Douglas D. Coolbaugh ,  Keith E. Downes ,  Peter J. Lindgren ,  Anthony K. Stamper

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L23/481 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76832 ,  H01L23/5223 ,  H01L28/60 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.

Abstract translation: 一种方法和半导体器件。 在该方法中，至少一个部分通孔被蚀刻成堆叠结构，围绕至少一个部分通孔形成边界。 该方法还包括使用选择性蚀刻执行厚布线，同时通过蚀刻继续至少一个蚀刻停止层。