公开(公告)号：US09401594B2

公开(公告)日：2016-07-26

申请号：US14374498

申请日：2012-02-15

Applicant: Quanqing Zhu ,  Guangming Yin

Inventor： Quanqing Zhu ,  Guangming Yin

IPC: H02H9/00 ,  H02H3/22 ,  H04L25/02

CPC classification number: H02H3/22 ,  H04L25/0272 ,  H04L25/028

Abstract: An integrated circuit device (200) includes a first and second differential I/O pins (TRXP/TRXN) and a surge protection circuit. The surge protection circuit includes a protection transistor, a positive surge detection circuit, and a negative surge detection circuit. The protection transistor is connected between the first and second I/O pins and has a gate to receive a control signal (CTRL). The protection transistor is turned on to connect the I/O pins together if the positive surge detection circuit detects a positive surge energy on either of the I/O pins and/or if the negative surge detection circuit detects a negative surge energy on either of the I/O pins. The surge protection circuit provides increased protection for Ethernet device against undesirable energy in a manner that does not adversely affect the performance of the device.

Abstract translation: 集成电路装置（200）包括第一和第二差分I / O引脚（TRXP / TRXN）和浪涌保护电路。 浪涌保护电路包括保护晶体管，正浪涌检测电路和负浪涌检测电路。 保护晶体管连接在第一和第二I / O引脚之间，并具有接收控制信号（CTRL）的门。 如果正浪涌检测电路检测到任一个I / O引脚上的正浪涌能量和/或如果负浪涌检测电路检测到任何一个的负浪涌能量，则保护晶体管导通以将I / O引脚连接在一起 I / O引脚。 浪涌保护电路以不会对设备性能产生不利影响的方式为以太网设备提供更高的防护性能，防止不需要的能量。

公开(公告)号：US08779859B2

公开(公告)日：2014-07-15

申请号：US13570062

申请日：2012-08-08

Applicant: Wenjun Su ,  Chiewcharn Narathong ,  Guangming Yin ,  Aristotele Hadjichristos

Inventor： Wenjun Su ,  Chiewcharn Narathong ,  Guangming Yin ,  Aristotele Hadjichristos

IPC: H03F1/22

CPC classification number: H03F1/223 ,  H03F3/193

Abstract: Techniques for generating bias voltages for a multi-cascode amplifier. In an aspect, a multi-cascode bias network is provided, each transistor in the bias network being a replica of a corresponding transistor in the multi-cascode amplifier, enabling accurate biasing of the transistors in the multi-cascode amplifier. In another aspect, a voltage supply for the multi-cascode amplifier is provided separately from a voltage supply for the replica bias network, to advantageously decouple variations in the amplifier voltage supply from the bias network voltage supply. In yet another aspect, the bias voltages of transistors in the multi-cascode amplifier may be configured by adjusting the impedance of resistive voltage dividers coupled to the transistor gate biases. As the gain of the amplifier depends on the bias voltages of the cascode amplifiers, the gain of the amplifier may be adjusted in this manner without introducing a variable gain element directly in the amplifier signal path.

Abstract translation: 用于产生多共源共栅放大器偏置电压的技术。 在一方面，提供了一种多共源共栅偏压网络，偏置网络中的每个晶体管是多共源共栅放大器中对应的晶体管的复制品，使多级共源共栅放大器中的晶体管能够精确偏置。 在另一方面，用于多重共源共栅放大器的电压源与用于复制偏压网络的电压源分开提供，以有利地将放大器电压源与偏置网络电压源的变化分离。 在另一方面，多并联放大器中的晶体管的偏置电压可以通过调整耦合到晶体管栅极偏置的电阻分压器的阻抗来配置。 由于放大器的增益取决于共源共栅放大器的偏置电压，所以可以以这种方式调节放大器的增益，而不将可变增益元件直接引入放大器信号路径。

公开(公告)号：US07142013B2

公开(公告)日：2006-11-28

申请号：US11133723

申请日：2005-05-20

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H03K19/21

CPC classification number: H03D13/003 ,  H03K19/215 ,  H04L7/033

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

公开(公告)号：US07135926B2

公开(公告)日：2006-11-14

申请号：US11239927

申请日：2005-09-29

Applicant: Mario Caresosa ,  Guangming Yin

Inventor： Mario Caresosa ,  Guangming Yin

IPC: H03F3/45

CPC classification number: H03F3/4569 ,  H03F3/45197 ,  H03F3/45744 ,  H03F2200/78 ,  H03F2203/45074 ,  H03F2203/45086 ,  H03F2203/45482 ,  H03F2203/45486 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

Abstract translation: 一种用于自适应地控制可变增益放大器（VGA）的方法和装置。 VGA的操作被分为低增益模式和高增益模式，并且自适应地感测VGA当前正在操作的模式。 将门限电压与VGA的控制电压进行比较; 如果VGA当前处于低增益模式并且控制电压高于阈值电压，则VGA从低增益模式切换到高增益模式; 如果VGA当前处于高增益模式并且控制电压低于阈值电压，则VGA从高增益模式切换到低增益模式。

公开(公告)号：US07034606B2

公开(公告)日：2006-04-25

申请号：US10841766

申请日：2004-05-07

Applicant: Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

Inventor： Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

IPC: G06G7/12

CPC classification number: H03G1/007 ,  H03F3/45188 ,  H03F3/45197 ,  H03F2203/45504 ,  H03F2203/45638 ,  H03G1/0029 ,  H03G1/0088

Abstract: An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At least one resistor is coupled between first terminals of the first and second input transistors. The input processing circuit includes a variable gain amplifier (VGA) circuit. At least one first transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. At least one second transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. A gate switch is coupled to the gate terminal of the at least one second transistor. The at least one first transistor and the at least one second transistor adjust a gain of the input processing circuit in response to a control voltage. The control voltage is applied to the gate terminal of the at least one first transistor, and the control voltage is applied to the gate terminal of the at least one second transistor through the gate switch.

Abstract translation: 输入处理电路包括分别用于接收第一和第二输入信号的差分对的第一和第二输入晶体管。 至少一个电阻耦合在第一和第二输入晶体管的第一端之间。 输入处理电路包括可变增益放大器（VGA）电路。 至少一个第一晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 至少一个第二晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 栅极开关耦合到至少一个第二晶体管的栅极端子。 所述至少一个第一晶体管和所述至少一个第二晶体管响应于控制电压调整所述输入处理电路的增益。 控制电压被施加到至少一个第一晶体管的栅极端子，并且通过栅极开关将控制电压施加到至少一个第二晶体管的栅极端子。

公开(公告)号：US06982583B2

公开(公告)日：2006-01-03

申请号：US10876790

申请日：2004-06-25

Applicant: Guangming Yin ,  Ichiro Fujimori ,  Armond Hairapetian

Inventor： Guangming Yin ,  Ichiro Fujimori ,  Armond Hairapetian

IPC: H03K3/356

CPC classification number: H03K3/3562 ,  H03K3/356043 ,  H03K17/693 ,  H03K19/09432 ,  H03K19/215

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract translation: 用于实现超高速电路的各种电路技术使用以常规CMOS工艺技术制造的电流控制CMOS（C 3/4 MOS）逻辑。 包括逆变器/缓冲器，电平移位器，NAND，NOR，异或门，锁存器，触发器等的整个逻辑元件族都使用C 3 MOS技术实现。 通过将高速C“3”MOS逻辑与低功耗常规CMOS逻辑相结合，实现了每个电路应用的功耗和速度之间的最佳平衡。 组合的三极管/ CMOS逻辑允许诸如光纤通信系统中使用的高速收发器之类的电路的更大集成。 C 3 O 3 MOS结构能够使用可能大于CMOS制造工艺所需的电压的电源电压，进一步提高电路的性能。

公开(公告)号：US06980053B2

公开(公告)日：2005-12-27

申请号：US10852275

申请日：2004-05-24

Applicant: Mario Caresosa ,  Guangming Yin

Inventor： Mario Caresosa ,  Guangming Yin

IPC: H03F3/45 ,  H03G1/00 ,  H03G3/30

CPC classification number: H03F3/4569 ,  H03F3/45197 ,  H03F3/45744 ,  H03F2200/78 ,  H03F2203/45074 ,  H03F2203/45086 ,  H03F2203/45482 ,  H03F2203/45486 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

Abstract translation: 一种用于自适应地控制可变增益放大器（VGA）的方法和装置。 VGA的操作被分为低增益模式和高增益模式，并且自适应地感测VGA当前正在操作的模式。 将门限电压与VGA的控制电压进行比较; 如果VGA当前处于低增益模式并且控制电压高于阈值电压，则VGA从低增益模式切换到高增益模式; 如果VGA当前处于高增益模式并且控制电压低于阈值电压，则VGA从高增益模式切换到低增益模式。

公开(公告)号：US20050258900A1

公开(公告)日：2005-11-24

申请号：US10852275

申请日：2004-05-24

Applicant: Mario Caresosa ,  Guangming Yin

Inventor： Mario Caresosa ,  Guangming Yin

IPC: H03F3/45 ,  H03G1/00 ,  H03G3/30

CPC classification number: H03F3/4569 ,  H03F3/45197 ,  H03F3/45744 ,  H03F2200/78 ,  H03F2203/45074 ,  H03F2203/45086 ,  H03F2203/45482 ,  H03F2203/45486 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

Abstract translation: 一种用于自适应地控制可变增益放大器（VGA）的方法和装置。 VGA的操作被分为低增益模式和高增益模式，并且自适应地感测VGA当前正在操作的模式。 将门限电压与VGA的控制电压进行比较; 如果VGA当前处于低增益模式并且控制电压高于阈值电压，则VGA从低增益模式切换到高增益模式; 如果VGA当前处于高增益模式并且控制电压低于阈值电压，则VGA从高增益模式切换到低增益模式。

公开(公告)号：US20050190004A1

公开(公告)日：2005-09-01

申请号：US11120738

申请日：2005-05-03

Applicant: Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

Inventor： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

IPC: H03B5/12 ,  H03L7/099 ,  H03L7/10 ,  H04J3/04 ,  H04J3/06 ,  H04L7/00 ,  H03B1/00

CPC classification number: H03L7/10 ,  H03B5/1209 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03L7/099 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

Abstract translation: 本发明提供了一种用于基于用于调谐诸如VCO的设备内的其它设备的设置来将输出驱动器调谐到工作频率的方法。 首先将PLL和时钟电路中的VCO调谐到所需的工作频率。 此工作频率对应于离散调谐设置。 导致VCO在工作频率下工作的离散设置随后被传送到输出驱动器内的缩放放大器。 然后通过这些设置将这些驱动程序调整到工作频率。 该过程无需单独调整每个输出驱动器在工作频率下正常工作。

公开(公告)号：US20050134310A1

公开(公告)日：2005-06-23

申请号：US11057968

申请日：2005-02-15

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H03D13/00 ,  H03F3/45 ,  H03K19/21 ,  H04L7/033

CPC classification number: H03D13/003 ,  H03K19/215 ,  H04L7/033

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.