公开(公告)号：US20110223752A1

公开(公告)日：2011-09-15

申请号：US12720075

申请日：2010-03-09

Applicant: Fung Ka HING ,  Haiting WANG ,  Han-Ting TSAI ,  Chun-Fai CHENG ,  Wei-Yuan LU ,  Hsien-Ching LO ,  Kuan-Chung CHEN

Inventor： Fung Ka HING ,  Haiting WANG ,  Han-Ting TSAI ,  Chun-Fai CHENG ,  Wei-Yuan LU ,  Hsien-Ching LO ,  Kuan-Chung CHEN

IPC: H01L21/28

CPC classification number: H01L29/7833 ,  H01L21/76834 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7836

Abstract: The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.

Abstract translation: 本公开公开了一种用于制造栅极结构的示例性方法，其包括在衬底上沉积和图案化虚拟氧化物层和伪栅极电极层; 围绕所述虚拟氧化物层和所述伪栅极电极层，具有牺牲层; 用含氮介电层围绕牺牲层; 用层间介质层包围含氮介电层; 去除所述伪栅电极层; 去除虚拟氧化物层; 去除所述牺牲层以在所述含氮介电层中形成开口; 并沉积栅极电介质; 并沉积栅电极。

公开(公告)号：US20110193167A1

公开(公告)日：2011-08-11

申请号：US12704367

申请日：2010-02-11

Applicant: Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

Inventor： Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

IPC: H01L27/12 ,  H01L27/105

CPC classification number: H01L27/1203 ,  H01L21/26506 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

Abstract: An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate.

Abstract translation: 集成电路结构包括包括有源区的半导体衬底。 第一浅沟槽隔离（STI）区域邻接有源区域的第一侧。 MOS器件的栅电极在有源区和第一STI区之上。 MOS器件的源极/漏极应力区域包括半导体衬底中的与栅电极相邻的部分。 在半导体衬底中形成沟槽，并与有源区域的第二面相邻。 沟槽的底部不低于源极/漏极区域的底部。 层间电介质（ILD）从栅极电极延伸到沟槽内部，其中沟槽中的ILD的一部分形成第二STI区域。 第二STI区域和源极/漏极应力区域彼此分离并邻接半导体衬底的一部分。

公开(公告)号：US20110079856A1

公开(公告)日：2011-04-07

申请号：US12571604

申请日：2009-10-01

Applicant: Ming-Huan Tsai ,  Han-Ting Tsai

Inventor： Ming-Huan Tsai ,  Han-Ting Tsai

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823418 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7848

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a surface of the substrate, and strained structures disposed in the substrate at either side of the gate structure and formed of a semiconductor material different from the semiconductor substrate. Each strained structure has a cross-sectional profile that includes a first portion that extends from the surface of substrate and a second portion that tapers from the first portion at an angle ranging from about 50° to about 70°. The angle is measured with respect to an axis parallel to the surface of the substrate.

Abstract translation: 本公开提供一种半导体器件，其包括半导体衬底，设置在衬底的表面上的栅极结构以及设置在栅极结构的任一侧的衬底中的应变结构，并且由与半导体衬底不同的半导体材料形成。 每个应变结构具有横截面轮廓，该截面轮廓包括从基底表面延伸的第一部分和从第一部分以约50°至约70°的角度逐渐变细的第二部分。 角度相对于平行于基板表面的轴线被测量。

公开(公告)号：US08815722B2

公开(公告)日：2014-08-26

申请号：US13274558

申请日：2011-10-17

Applicant: Ka-Hing Fung ,  Wei-Yuan Lu ,  Han-Ting Tsai

Inventor： Ka-Hing Fung ,  Wei-Yuan Lu ,  Han-Ting Tsai

IPC: H01L21/22 ,  H01L21/38

CPC classification number: H01L21/2257 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is formed over the at least one silicon-containing layer. The N-type doped silicon-containing layer has an N-type dopant concentration higher than that of the at least one silicon-containing layer. The N-type doped silicon-containing layer is annealed so as to drive N-type dopants of the N-type doped silicon-containing layer to the S/D regions.

Abstract translation: 形成集成电路的方法包括在衬底上形成栅极结构。 在与栅极结构的侧壁相邻的源极/漏极（S / D）区域中形成至少一个含硅层。 在至少一个含硅层上形成N型掺杂的含硅层。 N型掺杂含硅层的N型掺杂剂浓度高于至少一种含硅层。 对N型掺杂含硅层进行退火，以将N型掺杂含硅层的N型掺杂剂驱动到S / D区。

公开(公告)号：US20140021517A1

公开(公告)日：2014-01-23

申请号：US13551107

申请日：2012-07-17

Applicant: Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

Inventor： Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. An isolation structure is formed in a substrate and a gate stack is formed atop the isolation structure. A spacer is formed adjoining a sidewall of the gate stack and extends beyond an edge of the isolation structure. The disclosed method provides an improved method for protecting the isolation structure by using the spacer. The spacer can prevent the isolation structure from being damaged by chemicals, therefor, to enhance contact landing and upgrade the device performance.

Abstract translation: 公开了一种用于制造半导体器件的半导体器件和方法。 在衬底中形成隔离结构，并且在隔离结构的顶部形成栅叠层。 邻接栅叠层的侧壁并且延伸超出隔离结构的边缘的间隔件。 所公开的方法提供了通过使用间隔物来保护隔离结构的改进方法。 间隔件可以防止隔离结构被化学物质损坏，从而增强接触着陆和提升设备性能。

公开(公告)号：US08569139B2

公开(公告)日：2013-10-29

申请号：US12913041

申请日：2010-10-27

Applicant: Chun-Feng Nieh ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Yimin Huang ,  Chun-Fai Cheng ,  Han-Ting Tsai ,  Chii-Ming Wu

Inventor： Chun-Feng Nieh ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Yimin Huang ,  Chun-Fai Cheng ,  Han-Ting Tsai ,  Chii-Ming Wu

IPC: H01L21/336 ,  H01L21/461

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.

公开(公告)号：US08502316B2

公开(公告)日：2013-08-06

申请号：US12704367

申请日：2010-02-11

Applicant: Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

Inventor： Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

IPC: H01L29/72

CPC classification number: H01L27/1203 ,  H01L21/26506 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

Abstract: An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate.

Abstract translation: 集成电路结构包括包括有源区的半导体衬底。 第一浅沟槽隔离（STI）区域邻接有源区域的第一侧。 MOS器件的栅电极在有源区和第一STI区之上。 MOS器件的源极/漏极应力区域包括半导体衬底中的与栅电极相邻的部分。 在半导体衬底中形成沟槽，并与有源区域的第二面相邻。 沟槽的底部不低于源极/漏极区域的底部。 层间电介质（ILD）从栅极电极延伸到沟槽内部，其中沟槽中的ILD的一部分形成第二STI区域。 第二STI区域和源极/漏极应力区域彼此分离并邻接半导体衬底的一部分。

公开(公告)号：US20120108026A1

公开(公告)日：2012-05-03

申请号：US12913041

申请日：2010-10-27

Applicant: Chun-Feng NIEH ,  Ming-Huan TSAI ,  Wei-Han FAN ,  Yimin HUANG ,  Chun-Fai CHENG ,  Han-Ting TSAI ,  Chii-Ming WU

Inventor： Chun-Feng NIEH ,  Ming-Huan TSAI ,  Wei-Han FAN ,  Yimin HUANG ,  Chun-Fai CHENG ,  Han-Ting TSAI ,  Chii-Ming WU

IPC: H01L21/336

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。 掺杂区域注入与LDD区域相反的掺杂剂类型。

公开(公告)号：US20110291201A1

公开(公告)日：2011-12-01

申请号：US12787972

申请日：2010-05-26

Applicant: Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

Inventor： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括硅衬底。 半导体器件包括设置在衬底中的第一和第二区域。 第一和第二区域具有硅化合物材料。 半导体器件包括分别部分地设置在第一和第二区域中的第一和第二源/漏结构。 半导体器件包括设置在衬底上的第一栅极。 第一个门第一个靠近第一个地区。 半导体器件包括设置在衬底上的第二栅极。 第二个门第二个靠近第二个区域。 第二接近度不同于第一接近度。 第一源极/漏极结构和第一栅极是第一晶体管的部分，并且第二源极/漏极结构和第二栅极是第二晶体管的部分。

公开(公告)号：US20110193179A1

公开(公告)日：2011-08-11

申请号：US12716100

申请日：2010-03-02

Applicant: Ka-Hing Fung ,  Haiting Wang ,  Han-Ting Tsai

Inventor： Ka-Hing Fung ,  Haiting Wang ,  Han-Ting Tsai

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7848

Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The method involves providing a substrate; forming a gate structure over the substrate; forming an epitaxial layer in a source and drain region of the substrate that is interposed by the gate structure; and after forming the epitaxial layer, forming a lightly doped source and drain (LDD) feature in the source and drain region.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 该方法包括提供基底; 在衬底上形成栅极结构; 在由栅极结构插入的衬底的源极和漏极区域中形成外延层; 并且在形成外延层之后，在源极和漏极区域中形成轻掺杂的源极和漏极（LDD）特征。