公开(公告)号：US20120133425A1

公开(公告)日：2012-05-31

申请号：US13365935

申请日：2012-02-03

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G05F3/02

CPC分类号： H02M3/07

摘要： A booster circuit includes a pump circuit having a plurality of charge pump circuits that output a boosted voltage. The booster circuit also includes a clock adjusting circuit that generates a second clock signal for operating the charge pump circuits from a first clock signal to a first output terminal. The booster circuit additionally includes a pump controlling circuit that outputs the first clock signal for operating the pump circuit, a first comparator that outputs a first output signal, a second comparator that outputs a second output signal, and a third comparator that outputs a third output signal. A gradient of the boosted voltage is decreased when the first output signal is output. A frequency of the first clock signal is reduced when the second output signal is output. The third output signal is output when the boosted voltage is higher than a set value of the boosted voltage.

摘要翻译： 升压电路包括具有输出升压电压的多个电荷泵电路的泵电路。 升压电路还包括时钟调整电路，其产生用于将电荷泵电路从第一时钟信号操作到第一输出端的第二时钟信号。 升压电路还包括泵控制电路，其输出用于操作泵电路的第一时钟信号，输出第一输出信号的第一比较器，输出第二输出信号的第二比较器和输出第三输出的第三比较器 信号。 当输出第一输出信号时，升压电压的梯度减小。 当输出第二输出信号时，第一时钟信号的频率减小。 当升压电压高于升压电压的设定值时，输出第三输出信号。

公开(公告)号：US08159859B2

公开(公告)日：2012-04-17

申请号：US12720121

申请日：2010-03-09

申请人： Hiroshi Maejima

发明人： Hiroshi Maejima

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2213/72

摘要： A semiconductor storage device includes: a memory cell array including memory cells, each of the memory cells having a variable resistance element; and a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit a resistance state, to a selected memory cell. When applying the control voltage plural times, the control circuit operates to set a value of the control voltage applied in a first control voltage application operation to be substantially equal to a minimum value of distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element from a high resistance state to a low resistance state. The control circuit operates to perform a plurality of control voltage application operations by increasing the value of the control voltage by a certain value.

摘要翻译： 半导体存储装置包括：包括存储单元的存储单元阵列，每个存储单元具有可变电阻元件; 以及控制电路，被配置为将所述可变电阻元件所需的控制电压施加到选择的存储单元。 当多次施加控制电压时，控制电路操作以将在第一控制电压施加操作中施加的控制电压的值设置为基本上等于存储器中的所有存储器单元的电压值的分布的最小值 电池阵列需要将可变电阻元件的电阻状态从高电阻状态转移到低电阻状态。 控制电路通过将控制电压的值增加一定值来进行多个控制电压施加操作。

公开(公告)号：US20120075916A1

公开(公告)日：2012-03-29

申请号：US13315967

申请日：2011-12-09

申请人： Hideo MUKAI ,  Hiroshi MAEJIMA ,  Katsuaki ISOBE

发明人： Hideo MUKAI ,  Hiroshi MAEJIMA ,  Katsuaki ISOBE

IPC分类号： G11C11/00

CPC分类号： G11C8/14 ,  G11C7/18 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/72

摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.

摘要翻译： 一种非易失性半导体存储器件，包括具有以矩阵形式设置的多个MAT（单位阵列）的单元阵列，所述MAT各包括多条第一线，与第一线交叉的多条第二线，以及 存储单元连接在第一和第二线之间。 该装置还包括第一和第二驱动电路，选择连接到每个MAT的存储器单元的第一和第二线，所述存储器单元被访问，并且驱动所选择的第一和第二行来写入或读取数据。 存储单元通过连接到从MAT中选择的每个第一行形成页面。 该设备还包括以页为单位锁存写入或读取数据的数据锁存器，其中第一和第二驱动电路多次驱动第一和第二行以写入或读取单元阵列中的一页的数据。

公开(公告)号：US20120039110A1

公开(公告)日：2012-02-16

申请号：US13195417

申请日：2011-08-01

申请人： Hiroshi MAEJIMA ,  Koji Hosono

发明人： Hiroshi MAEJIMA ,  Koji Hosono

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066

摘要： A memory-cell array that includes a first line, a second line intersecting the first line, and a memory cell including a variable resistive element provided in the intersection of the first and the second lines; a data-write unit configured to apply a voltage pulse to the memory cell through the first and the second lines, the voltage pulse to set and/or reset data; and a detector unit configured to compare a cell current that flows through the memory cell by the voltage pulse at the time of setting and/or resetting the data with a reference current generated from the initial value of the cell current, and to control the data-write unit in accordance with a result of comparison.

摘要翻译： 包括第一行，与第一行相交的第二行的存储单元阵列和包括设置在第一和第二行的交叉点中的可变电阻元件的存储单元; 数据写入单元，被配置为通过第一和第二线路向存储器单元施加电压脉冲，电压脉冲以设置和/或复位数据; 以及检测器单元，被配置为将通过存储器单元流动的单元电流与在从单元电流的初始值生成的参考电流进行设置和/或重置数据时的电压脉冲进行比较，并且控制数据 根据比较结果写入单元。

公开(公告)号：US08102711B2

公开(公告)日：2012-01-24

申请号：US12953690

申请日：2010-11-24

申请人： Hiroshi Maejima

发明人： Hiroshi Maejima

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C5/02 ,  G11C5/063 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/3422

摘要： A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.

摘要翻译： 根据本发明的示例的三维堆叠的非易失性半导体存储器包括由第一和第二块组成的存储单元阵列。 第一块具有第一单元单元，其包括要编程的存储器单元和不包括要编程的存储单元的第二单元单元，并且通过将程序电位或转移电位施加到 在第一和第二单元单元中的存储器单元的通道的初始电位被设置为正电位之后的第一块。 在编程中，程序电位和转移电位不适用于第二个程序段中的字线。

公开(公告)号：US20120008371A1

公开(公告)日：2012-01-12

申请号：US13237405

申请日：2011-09-20

申请人： Hiroshi Maejima

发明人： Hiroshi Maejima

IPC分类号： G11C11/00

CPC分类号： G11C13/0023 ,  G11C5/025 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/71 ,  G11C2213/72

摘要： A semiconductor storage device includes: a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series; and a control circuit selectively driving the first and second wirings. The plurality of first wirings that are specified and selectively driven at the same time by one of a plurality of address signals are separately arranged with other first wirings interposed therebetween within the memory cell array when a certain potential difference is applied to a selected memory cell positioned at an intersection between the first and second wirings by the control circuit.

摘要翻译： 半导体存储装置包括：存储单元阵列，其具有位于多个第一布线与多个第二布线之间的各交叉点处的存储单元，每个存储单元具有串联连接的整流元件和可变电阻元件; 以及选择性地驱动第一和第二布线的控制电路。 通过多个地址信号中的一个同时被指定并有选择地驱动的多个第一布线与存储单元阵列中的其它第一布线分开布置，当将一定的电位差施加到所选择的存储单元时 在控制电路的第一和第二布线之间的交点处。

公开(公告)号：US08094477B2

公开(公告)日：2012-01-10

申请号：US12510798

申请日：2009-07-28

申请人： Hiroshi Maejima

发明人： Hiroshi Maejima

IPC分类号： G11C5/02

CPC分类号： G11C11/4087 ,  G11C8/08 ,  G11C8/10 ,  G11C13/00 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/72

摘要： A semiconductor storage device includes a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series, and a control circuit selectively driving the first and second wirings. The control circuit applies a first voltage to the selected first wiring and applies a second voltage to the selected second wiring to apply a certain potential difference to a selected memory cell positioned at a intersection between the selected first and second wirings, and brings at least one of nonselected first wirings into a floating state.

摘要翻译： 半导体存储装置包括具有存储单元的存储单元阵列，存储单元位于多条第一布线与多条第二布线之间的相交处，每个存储单元具有串联连接的整流元件和可变电阻元件， 电路选择性地驱动第一和第二布线。 所述控制电路对所选择的第一布线施加第一电压，并向所选择的第二布线施加第二电压，以向位于所选择的第一布线和第二布线之间的交叉点的选定存储单元施加一定的电位差，并且使至少一个 的未选择的第一条布线进入浮动状态。

公开(公告)号：US20110149653A1

公开(公告)日：2011-06-23

申请号：US13037965

申请日：2011-03-01

申请人： Hiroshi MAEJIMA ,  Katsuaki Isobe

发明人： Hiroshi MAEJIMA ,  Katsuaki Isobe

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0483

摘要： A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.

摘要翻译： 读取操作中的NAND闪速存储器设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电 位于接地电位和第一电压之间的第二电压，并且在未被所述行解码器选择的块中，所述漏极侧选择栅极线和所述源极侧选择栅极线被充电到第三电压，其中 高于所述接地电位，并且等于或低于所述第二电压。

公开(公告)号：US20110128774A1

公开(公告)日：2011-06-02

申请号：US13021398

申请日：2011-02-04

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G11C11/21 ,  G11C7/00

CPC分类号： G11C7/04 ,  G11C5/02 ,  G11C5/063 ,  G11C5/147 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch the variable resistor; and a clamp voltage generator circuit operative to generate a clamp voltage required for access to the memory cell and applied to the first and second lines. The clamp voltage generator circuit has a temperature compensation function of compensating for the temperature characteristic of the first non-ohmic element.

摘要翻译： 非易失性半导体存储器件包括存储单元阵列，其包括布置在第一和第二线的交点处的第一和第二相交线和电可擦除可编程存储器单元，每个存储单元包含可变电阻器，用于将其电阻非常地存储为数据， 用于切换可变电阻器的第一非欧姆元件; 以及钳位电压发生器电路，用于产生对存储单元的访问所需的钳位电压并施加到第一和第二线路。 钳位电压发生器电路具有补偿第一非欧姆元件的温度特性的温度补偿功能。

公开(公告)号：US20110116300A1

公开(公告)日：2011-05-19

申请号：US12885896

申请日：2010-09-20

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G11C11/21

CPC分类号： G11C8/08 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/72

摘要： A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell array including plural mutually crossing first and second lines and memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistance element and a rectifier element connected in series; and a data write/erase circuit operative to apply a voltage required for data write/erase to the memory cell via the first and second lines. The data write/erase circuit includes a first current limit circuit operative to limit the current flowing in the cathode-side line provided on the cathode side of the rectifier element, of the first and second lines, at the time of data write/erase.

摘要翻译： 根据实施例的非易失性半导体存储器件包括存储单元阵列，包括多个相互交叉的第一和第二线以及布置在第一和第二线的交点处的存储单元，每个存储单元包含可变电阻元件和串联连接的整流元件 ; 以及数据写入/擦除电路，用于经由第一和第二线路向存储器单元施加数据写/擦除所需的电压。 数据写入/擦除电路包括第一限流电路，用于限制在数据写/擦除时在第一和第二行的整流器元件的阴极侧设置的阴极侧线中流动的电流。