公开(公告)号：US07657713B2

公开(公告)日：2010-02-02

申请号：US10948674

申请日：2004-09-24

Applicant: Bok-Gue Park ,  Dong-Il Seo ,  Hyun-Soon Jang ,  Woo-Seop Jeong

Inventor： Bok-Gue Park ,  Dong-Il Seo ,  Hyun-Soon Jang ,  Woo-Seop Jeong

IPC: G06F13/14

CPC classification number: H04L12/56

Abstract: A memory that includes a plurality of packet pins, a synchronous memory, and a packet controller. The synchronous memory receives address and control signals in synchronization with a clock signal. The packet controller sequentially receives packet data bits through the packet pins in synchronization with the clock signal when a packet enable signal is activated, and converts the inputted packet data into the address and control signals. Specifically, packet data bits that are first inputted through the packet pins represent an operation mode.

Abstract translation: 包括多个分组引脚，同步存储器和分组控制器的存储器。 同步存储器与时钟信号同步地接收地址和控制信号。 当分组使能信号被激活时，分组控制器与时钟信号同步地通过分组引脚顺序地接收分组数据比特，并将输入的分组数据转换成地址和控制信号。 具体地，首先通过分组引脚输入的分组数据位表示操作模式。

公开(公告)号：US07566958B2

公开(公告)日：2009-07-28

申请号：US11589192

申请日：2006-10-30

Applicant: Byung-Se So ,  Dong-Ho Lee ,  Hyun-Soon Jang

Inventor： Byung-Se So ,  Dong-Ho Lee ,  Hyun-Soon Jang

IPC: H01L23/02

CPC classification number: H01L24/49 ,  G11C5/00 ,  G11C5/06 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01055 ,  H01L2924/01075 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.

Abstract translation: 多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/​​输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。 第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。 第一至第N半导体芯片的内部焊盘彼此耦合，例如经由安装在基板上的公共焊盘。 第一半导体芯片的输入/输出焊盘直接接收通过多芯片封装的相应引脚传输的输入/输出信号。 第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。 当信号以高速传输到引脚时，多芯片封装可以通过将引脚的寄生负载保持在至少单个芯片的电平来提高信号兼容性。 此外，当不需要高速传输的信号被施加到引脚时，可以根据预先存在的方法来封装半导体芯片。

公开(公告)号：US07148563B2

公开(公告)日：2006-12-12

申请号：US10722159

申请日：2003-11-26

Applicant: Byung-Se So ,  Dong-Ho Lee ,  Hyun-Soon Jang

Inventor： Byung-Se So ,  Dong-Ho Lee ,  Hyun-Soon Jang

IPC: H01L23/02

CPC classification number: H01L24/49 ,  G11C5/00 ,  G11C5/06 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01055 ,  H01L2924/01075 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal from a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other.

Abstract translation: 多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/​​输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。 第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。 第一至第N半导体芯片的内部焊盘彼此耦合，例如经由安装在基板上的公共焊盘。 第一半导体芯片的输入/输出焊盘直接从多芯片封装的相应引脚接收输入/输出信号。 第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。

公开(公告)号：US06992943B2

公开(公告)日：2006-01-31

申请号：US10959804

申请日：2004-10-06

Applicant: Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

Inventor： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

IPC: G11C7/00

CPC classification number: G11C11/40622 ,  G11C7/1018 ,  G11C11/406 ,  G11C11/4087

Abstract: Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or 1/16) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

公开(公告)号：US20050094631A1

公开(公告)日：2005-05-05

申请号：US10948674

申请日：2004-09-24

Applicant: Bok-Gue Park ,  Dong-Il Seo ,  Hyun-Soon Jang ,  Woo-Seop Jeong

Inventor： Bok-Gue Park ,  Dong-Il Seo ,  Hyun-Soon Jang ,  Woo-Seop Jeong

IPC: G11C11/409 ,  H04L12/56 ,  H04L12/66

CPC classification number: H04L12/56

Abstract: A memory that includes a plurality of packet pins, a synchronous memory, and a packet controller. The synchronous memory receives address and control signals in synchronization with a clock signal. The packet controller sequentially receives packet data bits through the packet pins in synchronization with the clock signal when a packet enable signal is activated, and converts the inputted packet data into the address and control signals. Specifically, packet data bits that are first inputted through the packet pins represent an operation mode.

Abstract translation: 包括多个分组引脚，同步存储器和分组控制器的存储器。 同步存储器与时钟信号同步地接收地址和控制信号。 当分组使能信号被激活时，分组控制器与时钟信号同步地通过分组引脚顺序地接收分组数据比特，并将输入的分组数据转换成地址和控制信号。 具体地，首先通过分组引脚输入的分组数据位表示操作模式。

公开(公告)号：US06510096B2

公开(公告)日：2003-01-21

申请号：US09981945

申请日：2001-10-17

Applicant: Jong-hyun Choi ,  Jei-hwan Yoo ,  Jong-eon Lee ,  Hyun-soon Jang

Inventor： Jong-hyun Choi ,  Jei-hwan Yoo ,  Jong-eon Lee ,  Hyun-soon Jang

IPC: G11C802

CPC classification number: G11C5/143 ,  G11C7/22

Abstract: A semiconductor device for controlling entry to and exit from a power down mode (DPD) of a semiconductor memory, comprising a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and for generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and circuitry for controlling the timing of turning on/off the plurality of voltage generators upon entry/exit of DPD mode to reduce surge current through the semiconductor memory to less than maximum current level.

公开(公告)号：US06343036B1

公开(公告)日：2002-01-29

申请号：US09157271

申请日：1998-09-18

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C700

CPC classification number: G11C7/1018 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平是第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的去激活信号，使得响应于激活信号的所选存储器组在活动周期中工作，而未被选择的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US06281745B1

公开(公告)日：2001-08-28

申请号：US09511848

申请日：2000-02-23

Applicant: Jae Hoon Kim ,  Hyun Soon Jang ,  Hoon Ryu

Inventor： Jae Hoon Kim ,  Hyun Soon Jang ,  Hoon Ryu

IPC: G05F302

CPC classification number: G05F1/465

Abstract: A flexible internal power supply voltage generating circuit of a semiconductor memory device includes a step-down circuit and a selection circuit. The selection circuit selects the step-down circuit for use when the semiconductor device uses a high external power supply voltage but bypasses the step-down circuit for a low external power supply voltage. One such circuit additionally includes a power supply terminal and a control circuit. The power supply terminal receives an external power supply voltage. The control circuit compares a feedback internal power supply voltage with a reference voltage at the time of driving a word line and then generates a control voltage signal for controlling a DIP of an internal power supply voltage caused by driving the word line. A selection circuit selectively connects a high voltage node or a low voltage node to the power supply terminal according to the external power supply voltage. The step-down circuit connects to the high voltage node and reduces the external power supply voltage when the power supply terminal receives the high supply voltage. The driver is between a common connection point of the step-down circuit and the low voltage node and an internal circuit and drives the external power supply voltage in the internal circuit in response to the control signal. Accordingly, when a high voltage is applied, the high voltage is stepped down and provided to the driver, thereby controlling a reverse overshoot of the internal power supply voltage.

Abstract translation: 半导体存储器件的柔性内部电源电压产生电路包括降压电路和选择电路。 选择电路选择半导体器件使用高外部电源电压时使用的降压电路，但是为了低的外部电源电压而绕过降压电路。 一个这样的电路还包括电源端子和控制电路。 电源端子接收外部电源电压。 控制电路将反馈内部电源电压与驱动字线时的参考电压进行比较，然后生成用于控制由驱动字线引起的内部电源电压的DIP的控制电压信号。 选择电路根据外部电源电压选择性地将高压节点或低压节点连接到电源端子。 当电源端子接收到高电源电压时，降压电路连接到高压节点并降低外部电源电压。 驱动器在降压电路的公共连接点和低电压节点之间以及内部电路之间，响应于控制信号驱动内部电路中的外部电源电压。 因此，当施加高电压时，高压被降低并提供给驱动器，从而控制内部电源电压的反向过冲。

公开(公告)号：US5535171A

公开(公告)日：1996-07-09

申请号：US383767

申请日：1995-02-03

Applicant: Chull-Soo Kim ,  Hyun-Soon Jang

Inventor： Chull-Soo Kim ,  Hyun-Soon Jang

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/417 ,  H03K3/356 ,  H03K19/0175 ,  G11C8/00

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  H03K3/35606

Abstract: A data output buffer of a semiconductor memory device using a clock having a fixed period from outside. The data output buffer has a data input part controlled and synchronized with a clock, for inputting data; a data latch device for latching data output through the data input part to thereby set up a predetermined delay time; a control signal input part controlled by the clock, for inputting a control signal; a latch controller for latching the control signal output through the control signal input part during a given time; a data output driver for receiving an output signal from the data latch device, the data output driver being controlled by the output signal of the latch controller; and an output device connected to the data output driver, for providing the data.

Abstract translation: 一种半导体存储器件的数据输出缓冲器，其使用具有从外部固定周期的时钟。 数据输出缓冲器具有控制并与时钟同步的数据输入部分，用于输入数据; 数据锁存装置，用于锁存通过数据输入部分输出的数据，从而建立预定的延迟时间; 由时钟控制的用于输入控制信号的控制信号输入部; 锁定控制器，用于锁定在给定时间内通过控制信号输入部分输出的控制信号; 数据输出驱动器，用于从数据锁存装置接收输出信号，数据输出驱动器由锁存控制器的输出信号控制; 以及连接到数据输出驱动器的输出设备，用于提供数据。

公开(公告)号：US07941714B2

公开(公告)日：2011-05-10

申请号：US12003900

申请日：2008-01-03

Applicant: Yong-hwan Cho ,  Kwun-soo Cheon ,  Hyun-soon Jang ,  Seung-whan Seo

Inventor： Yong-hwan Cho ,  Kwun-soo Cheon ,  Hyun-soon Jang ,  Seung-whan Seo

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/40 ,  G11C5/04 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  G11C2029/2602

Abstract: A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.

Abstract translation: 包含在堆叠在多芯片封装（MCP）中并且共享一组数据信号线的存储器芯片中的并行位测试（PBT）装置可以包括：比较单元，用于输出表示比较的数据信号 分别提供给给定的一个存储器芯片的测试数据信号和从其输出的相应的数据信号之间; 以及编码单元，用于使用所述共享数据信号线组的第一子集输出所述代表数据信号，所述第一子集分别不与由所述存储器芯片中的其他存储器芯片对应的编码单元使用的其他子集重叠，所述编码单元选择 根据第一测试模式寄存器组（MRS）信号将数据信号线的共享数据集中的一个或多个数据信号线包括在第一子集中。