公开(公告)号：US20120153796A1

公开(公告)日：2012-06-21

申请号：US13324492

申请日：2011-12-13

Applicant: Jeong Su HAN ,  In Sang Jeon ,  Duke Kimm ,  Kwang Hoon Lee ,  Sung Soo Lee ,  Jung Bae Kim ,  Hyung Jin Seo ,  Song Kyoo Kim ,  Jin Ha Jeong

Inventor： Jeong Su HAN ,  In Sang Jeon ,  Duke Kimm ,  Kwang Hoon Lee ,  Sung Soo Lee ,  Jung Bae Kim ,  Hyung Jin Seo ,  Song Kyoo Kim ,  Jin Ha Jeong

IPC: F25D23/06 ,  B65D81/38

CPC classification number: F25D25/005 ,  F25D2323/021

Abstract: A refrigerator includes a main body, a storage compartment provided in the main body and including a storage space, a partition plate to divide the storage space, and a storage container supported by the partition plate. The storage container includes a container body defining the external appearance of the storage container and having a top opening, a thickness reinforced portion formed at the lower part of the container body to prevent temperature of the lower part of the container body from rapidly changing by cold air of the storage compartment, and a thermal insulating member provided in a space between the thickness reinforced portion and the container body.

Abstract translation: 冰箱包括主体，设置在主体中的储藏室，并且包括存储空间，分隔存储空间的分隔板和由分隔板支撑的存储容器。 储存容器包括限定存储容器的外观并具有顶部开口的容器主体，形成在容器主体的下部的厚度增强部分，以防止容器主体的下部的温度由于冷而快速变化 储存室的空气和设置在厚度增强部分和容器主体之间的空间中的绝热构件。

公开(公告)号：US07692196B2

公开(公告)日：2010-04-06

申请号：US11655689

申请日：2007-01-19

Applicant: In-Sang Jeon ,  Sang-Bom Kang ,  Dong-Chan Kim ,  Chul-Sung Kim ,  Sug-Hun Hong ,  Sang-Jin Hyun

Inventor： In-Sang Jeon ,  Sang-Bom Kang ,  Dong-Chan Kim ,  Chul-Sung Kim ,  Sug-Hun Hong ,  Sang-Jin Hyun

IPC: H01L27/108

CPC classification number: H01L21/28282 ,  H01L29/513 ,  H01L29/792 ,  Y10S257/908

Abstract: The memory device includes a first tunnel insulation layer pattern on a semiconductor substrate, a second tunnel insulation layer pattern having an energy band gap lower than that of the first tunnel insulation layer pattern on the first tunnel insulation layer pattern, a charge trapping layer pattern on the second tunnel insulation layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode on the blocking layer pattern. The memory device further includes a source/drain region at an upper portion of the semiconductor substrate. The upper portion of the semiconductor substrate is adjacent to the first tunnel insulation layer pattern.

Abstract translation: 存储器件包括在半导体衬底上的第一隧道绝缘层图案，第二隧道绝缘层图案，其第一隧道绝缘层图案上具有比第一隧道绝缘层图案低的能带隙， 第二隧道绝缘层图案，电荷俘获层图案上的阻挡层图案，以及阻挡层图案上的栅电极。 存储器件还包括在半导体衬底的上部的源极/漏极区域。 半导体衬底的上部与第一隧道绝缘层图案相邻。

公开(公告)号：US20090134448A1

公开(公告)日：2009-05-28

申请号：US12230835

申请日：2008-09-05

Applicant: Taek-Soo Jeon ,  Si-Young Choi ,  In-Sang Jeon ,  Sang-Bom Kang ,  Si-Hyung Lee ,  Seung-Hoon Hong

Inventor： Taek-Soo Jeon ,  Si-Young Choi ,  In-Sang Jeon ,  Sang-Bom Kang ,  Si-Hyung Lee ,  Seung-Hoon Hong

IPC: H01L29/68 ,  H01L21/336

CPC classification number: H01L29/4234 ,  H01L29/40117

Abstract: Example embodiments provide a non-volatile semiconductor memory device and method of forming the same. The non-volatile memory device may include a tunnel insulation layer on a semiconductor substrate, a charge storage layer on the tunnel insulation layer, a first blocking insulation layer on the charge storage layer, and a gate electrode on the first blocking insulation layer, wherein the gate electrode includes aluminum and the first blocking insulation layer does not include aluminum.

Abstract translation: 示例性实施例提供了一种非易失性半导体存储器件及其形成方法。 非易失性存储器件可以包括半导体衬底上的隧道绝缘层，隧道绝缘层上的电荷存储层，电荷存储层上的第一阻挡绝缘层和第一阻挡绝缘层上的栅电极，其中 栅电极包括铝，并且第一阻挡绝缘层不包括铝。

公开(公告)号：US20100240180A1

公开(公告)日：2010-09-23

申请号：US12725743

申请日：2010-03-17

Applicant: In-Sang Jeon ,  Si-Hyung Lee ,  Jong-Ryeol Yoo ,  Yu-Gyun Shin ,  Suk-Hun Choi

Inventor： In-Sang Jeon ,  Si-Hyung Lee ,  Jong-Ryeol Yoo ,  Yu-Gyun Shin ,  Suk-Hun Choi

IPC: H01L21/336 ,  H01L21/8242

CPC classification number: H01L29/4236 ,  H01L21/67207 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/66621 ,  H01L29/78

Abstract: In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern.

Abstract translation: 在制造半导体器件的方法中，在衬底的有源区中形成凹部。 在第一凹部中形成栅极绝缘层。 在栅绝缘层上形成阻挡层。 在阻挡层上形成具有第一电阻的预成核层。 将初始成核层转变成具有比第一电阻显着小的第二电阻的成核层。 在成核层上形成导电层。 所述导电层，所述成核层，阻挡层和该栅极绝缘层被部分地蚀刻，以形成包括栅极绝缘层图案，阻挡层图案，一个成核层图案和导电层图案的埋入栅极结构。

公开(公告)号：US20070063295A1

公开(公告)日：2007-03-22

申请号：US11522343

申请日：2006-09-18

Applicant: In-Sang Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hong-Bae Park ,  Hye-Min Kim ,  Beom-Jun Jin

Inventor： In-Sang Jeon ,  Yu-Gyun Shin ,  Sang-Bom Kang ,  Hong-Bae Park ,  Hye-Min Kim ,  Beom-Jun Jin

IPC: H01L29/94

CPC classification number: H01L29/4983 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Example embodiments relate to a gate electrode, a method of forming the gate electrode, a transistor having the gate electrode, a method of manufacturing the transistor, a semiconductor device having the transistor and a method of manufacturing the semiconductor device. The gate electrode may include an embossing structure including a metal or a metal compound and having a first work function and a conductive layer pattern having a second work function formed on the embossing structure. A work function of the gate electrode may be adjusted between a work function of the embossing structure and a work function of the conductive layer pattern formed on the embossing structure. An NMOS transistor and a PMOS transistor having different work functions respectively may be formed on a substrate.

Abstract translation: 示例性实施例涉及栅电极，形成栅电极的方法，具有栅电极的晶体管，制造晶体管的方法，具有晶体管的半导体器件和制造半导体器件的方法。 栅电极可以包括包括金属或金属化合物并具有第一功函数的压花结构和在压花结构上形成的具有第二功函数的导电层图案。 可以在压花结构的功函数和形成在压花结构上的导电层图案的功函数之间调整栅电极的功函数。 可以在衬底上形成具有不同功函数的NMOS晶体管和PMOS晶体管。

公开(公告)号：US06590251B2

公开(公告)日：2003-07-08

申请号：US09911313

申请日：2001-07-23

Applicant: Sang-bom Kang ,  Hyun-seok Lim ,  Yung-sook Chae ,  In-sang Jeon ,  Gil-heyun Choi

Inventor： Sang-bom Kang ,  Hyun-seok Lim ,  Yung-sook Chae ,  In-sang Jeon ,  Gil-heyun Choi

IPC: H01L27108

CPC classification number: C23C16/34 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/7687 ,  H01L28/75

Abstract: Semiconductor films include insulating films including contact holes in semiconductor substrates, capacitors comprising lower electrodes formed on conductive material films in the contact holes, high dielectric films formed on the lower electrodes and upper electrodes formed on the high dielectric films, and barrier metal layers positioned between conductive materials in the contact holes and the lower electrodes, the barrier metal layers including metal layers formed in A-B-N structures in which a plurality of atomic layers are stacked by alternatively depositing reactive metal (A), an amorphous combination element (B) for preventing crystallization of the reactive metal (A) and nitrogen (N). The composition ratios of the barrier metal layers are determined by the number of depositions of the atomic layers.

Abstract translation: 半导体膜包括在半导体衬底中包括接触孔的绝缘膜，包括形成在接触孔中的导电材料膜上的下电极的电容器，形成在下电极上的高电介质膜和形成在高电介质膜上的上电极，以及位于 接触孔和下电极中的导电材料，阻挡金属层包括通过交替沉积反应性金属（A）而堆叠多个原子层的ABN结构中形成的金属层，用于防止结晶的非晶态组合元件（B） 的反应性金属（A）和氮（N）。 阻挡金属层的组成比由原子层的沉积数确定。

公开(公告)号：US20080116530A1

公开(公告)日：2008-05-22

申请号：US11855413

申请日：2007-09-14

Applicant: Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeon ,  Sang-bom Kang ,  Hye-min Kim

Inventor： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeon ,  Sang-bom Kang ,  Hye-min Kim

IPC: H01L29/94 ,  H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66621

Abstract: A semiconductor device may include a semiconductor substrate and first and second transistors. The first transistor may have a first gate structure on the semiconductor substrate, and the first gate structure may include a first gate insulating layer between a first gate electrode and the semiconductor substrate. The first gate insulating layer may include first and second dielectric materials with the second dielectric material having a greater dielectric constant than the first dielectric material. Moreover, the first gate electrode may be in contact with the second dielectric material. The second transistor may have a second gate structure on the semiconductor substrate, with the second gate structure including a second gate insulating layer between a second gate electrode and the semiconductor substrate. Related methods are also discussed.

Abstract translation: 半导体器件可以包括半导体衬底和第一和第二晶体管。 第一晶体管可以在半导体衬底上具有第一栅极结构，并且第一栅极结构可以包括在第一栅极电极和半导体衬底之间的第一栅极绝缘层。 第一栅极绝缘层可以包括第一和第二介电材料，其中第二介电材料具有比第一介电材料更大的介电常数。 此外，第一栅电极可以与第二电介质材料接触。 第二晶体管可以在半导体衬底上具有第二栅极结构，其中第二栅极结构包括在第二栅电极和半导体衬底之间的第二栅极绝缘层。 还讨论了相关方法。

公开(公告)号：US20070032008A1

公开(公告)日：2007-02-08

申请号：US11494100

申请日：2006-07-27

Applicant: Hye-Min Kim ,  Yu-Gyun Shin ,  In-Sang Jeon ,  Sang-Bom Kang ,  Hong-Bae Park ,  Beom-Jun Jin

Inventor： Hye-Min Kim ,  Yu-Gyun Shin ,  In-Sang Jeon ,  Sang-Bom Kang ,  Hong-Bae Park ,  Beom-Jun Jin

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

Abstract: A semiconductor device includes a substrate divided into an NMOS region and a PMOS region, a first gate pattern formed on the PMOS region, and a second gate pattern formed on the NMOS region. The first gate pattern includes a first gate oxide layer pattern, a metal oxide layer pattern, a silicon nitride layer pattern and a first polysilicon layer pattern that are sequentially stacked. The second gate pattern includes a second oxide layer pattern and a second polysilicon layer pattern. Related methods are also provided.

Abstract translation: 半导体器件包括分为NMOS区和PMOS区的衬底，形成在PMOS区上的第一栅极图案，以及形成在NMOS区上的第二栅极图案。 第一栅极图案包括依次层叠的第一栅极氧化物层图案，金属氧化物层图案，氮化硅层图案和第一多晶硅层图案。 第二栅极图案包括第二氧化物层图案和第二多晶硅层图案。 还提供了相关方法。