公开(公告)号：US20120153796A1

公开(公告)日：2012-06-21

申请号：US13324492

申请日：2011-12-13

申请人： Jeong Su HAN ,  In Sang Jeon ,  Duke Kimm ,  Kwang Hoon Lee ,  Sung Soo Lee ,  Jung Bae Kim ,  Hyung Jin Seo ,  Song Kyoo Kim ,  Jin Ha Jeong

发明人： Jeong Su HAN ,  In Sang Jeon ,  Duke Kimm ,  Kwang Hoon Lee ,  Sung Soo Lee ,  Jung Bae Kim ,  Hyung Jin Seo ,  Song Kyoo Kim ,  Jin Ha Jeong

IPC分类号： F25D23/06 ,  B65D81/38

CPC分类号： F25D25/005 ,  F25D2323/021

摘要： A refrigerator includes a main body, a storage compartment provided in the main body and including a storage space, a partition plate to divide the storage space, and a storage container supported by the partition plate. The storage container includes a container body defining the external appearance of the storage container and having a top opening, a thickness reinforced portion formed at the lower part of the container body to prevent temperature of the lower part of the container body from rapidly changing by cold air of the storage compartment, and a thermal insulating member provided in a space between the thickness reinforced portion and the container body.

摘要翻译： 冰箱包括主体，设置在主体中的储藏室，并且包括存储空间，分隔存储空间的分隔板和由分隔板支撑的存储容器。 储存容器包括限定存储容器的外观并具有顶部开口的容器主体，形成在容器主体的下部的厚度增强部分，以防止容器主体的下部的温度由于冷而快速变化 储存室的空气和设置在厚度增强部分和容器主体之间的空间中的绝热构件。

公开(公告)号：US07495968B2

公开(公告)日：2009-02-24

申请号：US11317079

申请日：2005-12-27

申请人： Sung Soo Lee ,  Min Su Kim ,  Seung Jae Lee

发明人： Sung Soo Lee ,  Min Su Kim ,  Seung Jae Lee

IPC分类号： G11C7/10

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3454

摘要： Disclosed is a page buffer having a wired-OR type structure and a cache function which is adapted for use in a nonvolatile semiconductor memory device and a method of programming same. The page buffer embeds the cache latch block in relation to the cache function. Moreover, the nonvolatile semiconductor memory device includes an output driver enabling an internal output line to be unidirectional driven, thereby enabling a program-verifying operation using the wired-OR scheme.

摘要翻译： 公开了一种适用于非易失性半导体存储器件的线或OR型结构和高速缓存功能的页缓冲器及其编程方法。 页面缓冲区相对于缓存功能嵌入高速缓存锁存块。 此外，非易失性半导体存储器件包括能够使内部输出线单向驱动的输出驱动器，从而能够进行使用有线方案的程序验证操作。

公开(公告)号：US08874934B2

公开(公告)日：2014-10-28

申请号：US12711458

申请日：2010-02-24

申请人： Jung Hoon Park ,  Sung Soo Lee

发明人： Jung Hoon Park ,  Sung Soo Lee

IPC分类号： G06F12/14 ,  H04L29/06 ,  G08B29/00 ,  G06F12/00 ,  G11C16/22

CPC分类号： G11C16/22

摘要： Disclosed is an operating method of a non-volatile memory device which comprises randomizing data to store the randomized data; erasing the randomized data; and outputting erase data according to information of a flag cell of the non-volatile memory device at a read operation.

摘要翻译： 公开了一种非易失性存储器件的操作方法，其包括随机化数据以存储随机数据; 擦除随机数据; 以及在读取操作时根据所述非易失性存储器件的标志单元的信息输出擦除数据。

公开(公告)号：US08514621B2

公开(公告)日：2013-08-20

申请号：US13089639

申请日：2011-04-19

申请人： Ki Hwan Choi ,  Sung Soo Lee ,  Jae-Woo Park ,  Sang-Hyun Joo

发明人： Ki Hwan Choi ,  Sung Soo Lee ,  Jae-Woo Park ,  Sang-Hyun Joo

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3436

摘要： A programming method for a nonvolatile memory device includes performing a LSB programming operation programming all LSB logical pages, and thereafter performing a MSB programming operation programming all MSB logical pages, wherein during the LSB programming operation a selected MLC is programmed to a negative intermediate program state. A program sequence for the LSB and MSB programming operations may be sequential or non-sequential in relation to an order arranged of word lines.

摘要翻译： 用于非易失性存储器件的编程方法包括执行编程所有LSB逻辑页的LSB编程操作，并且此后执行MSB编程操作编程所有MSB逻辑页，其中在LSB编程操作期间，所选择的MLC被编程为负的中间程序状态 。 用于LSB和MSB编程操作的程序序列可以是与字线布置的顺序相关或非顺序的。

公开(公告)号：US07480177B2

公开(公告)日：2009-01-20

申请号：US11870528

申请日：2007-10-11

申请人： Sung Soo Lee ,  Young Ho Lim ,  Hyun Chul Cho ,  Dong Hyuk Chae

发明人： Sung Soo Lee ,  Young Ho Lim ,  Hyun Chul Cho ,  Dong Hyuk Chae

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5642

摘要： According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line. The memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode.

摘要翻译： 根据一个方面，存储单元阵列包括连接到多个非易失性存储单元的位线，其中非易失性存储单元可选择性地以至少第一，第二，第三和第四阈值电压状态中的任何一个编程，并且其中 第一，第二，第三和第四阈值电压状态对应于由第一和第二位定义的四个不同的数据值。 页面缓冲电路将逻辑值存储为主锁存数据，并且响应于主锁存信号，以根据位线的电压电平选择性地翻转主锁存数据的逻辑值。 子锁存电路将逻辑值存储为子锁存数据，并且响应于子锁存信号，以根据位线的电压电平选择性地翻转子锁存数据的逻辑值。 存储器件可读取读取非易失性存储器单元的阈值电压状态的读取模式和编程非易失性存储器单元的阈值电压状态的编程模式，其中页面缓冲器电路有选择地响应于 子锁存数据，以禁止在编程模式下翻转主锁存器数据的逻辑值。

公开(公告)号：US20080206567A1

公开(公告)日：2008-08-28

申请号：US11794634

申请日：2005-12-28

申请人： Byung Hoon Min ,  Kyung Heum Kim ,  Seung Bum Kim ,  Sung Soo Lee ,  Kyoung Bae Park ,  Nam Gyol Kim ,  Byoung Jae Yoo

发明人： Byung Hoon Min ,  Kyung Heum Kim ,  Seung Bum Kim ,  Sung Soo Lee ,  Kyoung Bae Park ,  Nam Gyol Kim ,  Byoung Jae Yoo

IPC分类号： B05D5/12 ,  B32B15/02 ,  B32B37/02 ,  C25D5/00 ,  C25D3/12 ,  B32B37/24

CPC分类号： H01B1/02 ,  C23C18/1635 ,  C23C18/1641 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/285 ,  C23C18/30 ,  C23C18/36 ,  C23C18/405 ,  C23C28/00 ,  C23C28/021 ,  C23C28/023 ,  C25D3/60 ,  C25D7/00 ,  C25D17/20 ,  H01L23/49816 ,  H01L24/01 ,  H01L24/80 ,  H01L2224/2939 ,  H01L2224/294 ,  H01L2224/2989 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/0212 ,  H05K2201/0221 ,  Y02P70/613 ,  Y10T428/2991 ,  Y10T428/2993 ,  H01L2924/00

摘要： Plastic conductive particles having an outer diameter of 2.5 μm˜1 mm obtained by sequentially plating a 0.1˜10 μm thick metal plating layer and a 1˜100 μm thick Pb solder layer or a Pb-free solder layer on plastic core beads having a high elastic modulus of compression, and a method of manufacturing thereof. The method of manufacturing the plastic conductive particles includes preparing plastic core beads having excellent thermal properties and a high elastic modulus of compression, etching surfaces of the plastic core beads for surface treatment thereof, forming a metal plating layer via electroless plating to improve adhesion between the bead surface and the metal plating layer, and then forming a solder layer such that a sealed hexagonal barrel is immersed in an electroplating solution and then an electroplating process is conducted using a mesh barrel rotating 360° at 6˜10 rpm or a mesh barrel having a structure in which one surface of a conventional sealed hexagonal barrel is open, and rotating 200° in right and left directions at 1˜5 rpm, to manufacture plastic conductive particles having a size of 1 mm or less. The plastic conductive particles of this invention enable the maintenance of packaging gaps, and thus can be applied to IC packaging, LCD packaging and other conductive materials.

摘要翻译： 通过在具有高的塑料芯珠上顺序镀覆0.1〜10μm厚的金属镀层和1〜100μm厚的Pb焊料层或无铅焊料层，得到外径为2.5μm〜1mm的塑料导电性颗粒 弹性模量，及其制造方法。 制造塑料导电颗粒的方法包括制备具有优异的热性能和高弹性模量的塑性芯珠，用于表面处理的塑料芯珠的蚀刻表面，通过无电镀形成金属镀层，以改善 珠表面和金属镀层，然后形成焊接层，使得将密封的六边形圆筒浸入电镀溶液中，然后使用以6〜10rpm旋转360°的网筒进行电镀工艺，或者具有 常规密封六角筒的一个表面打开并以1〜5rpm左右旋转200度左右的结构，制造尺寸为1mm以下的塑料导电性粒子。 本发明的塑料导电颗粒能够保持包装间隙，因此可以应用于IC封装，LCD封装和其他导电材料。

公开(公告)号：US06380992B1

公开(公告)日：2002-04-30

申请号：US09276446

申请日：1999-03-25

申请人： Sung Soo Lee

发明人： Sung Soo Lee

IPC分类号： G02F11345

CPC分类号： G02F1/1309 ,  G02F2001/136263

摘要： A method for forming a defective pad repair structure in a liquid crystal display device having a plurality of pads disposed on a substrate. At least one defective pad repair line is provided to oppose the pads with an insulating layer disposed between the pads and the defective pad repair line. When at least one of the pads is broken, the broken pad can be restored by connecting the broken pad to the repair line by a welding process.

摘要翻译： 一种用于在具有设置在基板上的多个焊盘的液晶显示装置中形成有缺陷的焊盘修复结构的方法。 提供至少一个有缺陷的焊盘修补线以与焊盘相对，该绝缘层设置在焊盘和有缺陷的焊盘修补线之间。 当至少一个焊盘断裂时，可以通过焊接工艺将损坏的焊盘连接到修理线上来恢复破损的焊盘。

公开(公告)号：US06184948B2

公开(公告)日：2001-02-06

申请号：US09005587

申请日：1998-01-12

申请人： Sung Soo Lee

发明人： Sung Soo Lee

IPC分类号： G02F11333

CPC分类号： G02F1/13458 ,  G02F1/136286 ,  G02F2001/136254

摘要： A method for manufacturing a liquid crystal display device on a substrate including the steps of forming a gate electrode, a gate line, a gate pad, a source pad, a first gate shorting bar, and a first source shorting bar using a first metal; forming a gate insulation layer, a semiconductor layer, and a doped semiconductor layer by sequentially depositing an insulation material, an intrinsic semiconductor material, and a doped semiconductor material, respectively; and forming a source electrode, a source line, a drain electrode, a second gate shorting bar, and a second source shorting bar using a second metal.

摘要翻译： 一种在基板上制造液晶显示装置的方法，包括以下步骤：使用第一金属形成栅极，栅极线，栅极焊盘，源极焊盘，第一栅极短路棒和第一源极短路棒; 通过分别依次沉积绝缘材料，本征半导体材料和掺杂半导体材料来形成栅绝缘层，半导体层和掺杂半导体层; 以及使用第二金属形成源电极，源极线，漏电极，第二栅极短路棒和第二源极短路棒。

公开(公告)号：US07872925B2

公开(公告)日：2011-01-18

申请号：US12354915

申请日：2009-01-16

申请人： Sung Soo Lee ,  Min Su Kim ,  Seung Jae Lee

发明人： Sung Soo Lee ,  Min Su Kim ,  Seung Jae Lee

IPC分类号： G11C7/10

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3454

摘要： Disclosed is a page buffer having a wired-OR type structure and a cache function which is adapted for use in a nonvolatile semiconductor memory device and a method of programming same. The page buffer embeds the cache latch block in relation to the cache function. Moreover, the nonvolatile semiconductor memory device includes an output driver enabling an internal output line to be unidirectional driven, thereby enabling a program-verifying operation using the wired-OR scheme.

摘要翻译： 公开了一种适用于非易失性半导体存储器件的线或OR型结构和高速缓存功能的页缓冲器及其编程方法。 页面缓冲区相对于缓存功能嵌入高速缓存锁存块。 此外，非易失性半导体存储器件包括能够使内部输出线单向驱动的输出驱动器，从而能够进行使用有线方案的程序验证操作。

公开(公告)号：US07738297B2

公开(公告)日：2010-06-15

申请号：US12036416

申请日：2008-02-25

申请人： Oh Suk Kwon ,  Sung Soo Lee ,  Duck Kyeun Woo

发明人： Oh Suk Kwon ,  Sung Soo Lee ,  Duck Kyeun Woo

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G06F13/1647

摘要： A method and apparatus for controlling two or more non-volatile memory devices includes activating a read enable signal or a write enable signal, which is input to the first and second non-volatile memory devices, using a controller. A first chip enable signal is alternately activated for selecting the first non-volatile memory device and a second chip enable signal is activated for selecting the second non-volatile memory device using the controller. This is done while the read enable signal or the write enable signal is input to the first and second non-volatile memory devices being activated. Accordingly, even when the minimum cycle of the controller is longer than that of a memory device read/write time is reduced, thereby improving read/write performance.

摘要翻译： 用于控制两个或多个非易失性存储器件的方法和装置包括使用控制器激活输入到第一和第二非易失性存储器件的读使能信号或写使能信号。 交替激活第一芯片使能信号以选择第一非易失性存储器件，并激活第二芯片使能信号，以使用控制器选择第二非易失性存储器件。 这是在将读取使能信号或写入使能信号输入到被激活的第一和第二非易失性存储器件时完成的。 因此，即使当控制器的最小周期长于存储器件的最小周期时，读/写时间也减少，从而提高读/写性能。