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    Method of making self-aligned borderless contacts
    12.
    发明授权
    Method of making self-aligned borderless contacts 失效
    制定自主对边无边界联系的方法

    公开(公告)号：US06806177B2

    公开(公告)日：2004-10-19

    申请号：US10719861

    申请日：2003-11-21

    Applicant: Jay W. Strane ,  Hiroyuki Akatsu ,  David M. Dobuzinsky

    Inventor： Jay W. Strane ,  Hiroyuki Akatsu ,  David M. Dobuzinsky

    IPC: H01L2144

    CPC classification number: H01L21/76897

    Abstract: A method for forming high-density self-aligned contacts and interconnect structures in a semiconductor device. A dielectric layer thick enough to contain both interconnect and contact structures is formed on a substrate. A patterned hardmask is formed on the dielectric layer to define both the interconnect and contact structures. The openings for interconnect features are first formed by partially etching the dielectric layer selective to the hardmask. A second mask (e.g., a resist) is used to define the contact openings, and the dielectric layer is etched through the second mask, also selective to the hardmask, to expose the diffusion regions to be contacted. The patterned hardmask is used to help define the contact openings. Conductive material is then deposited in the openings which results in contacts and interconnects that are self-aligned. By first forming the openings for both interconnect and contacts, savings in processing steps may be obtained.

    Abstract translation: 一种在半导体器件中形成高密度自对准触点和互连结构的方法。 在衬底上形成足够厚以容纳互连和接触结构的电介质层。 在电介质层上形成图形化的硬掩模以限定互连和接触结构。 用于互连特征的开口首先通过部分蚀刻对硬掩模有选择性的介电层而形成。 使用第二掩模（例如抗蚀剂）来限定接触开口，并且通过第二掩模蚀刻电介质层，也可以对硬掩模进行选择，以暴露待接触的扩散区域。 图案化的硬掩模用于帮助定义接触开口。 然后将导电材料沉积在开口中，这导致自对准的触点和互连。 通过首先形成用于互连和接触的开口，可以获得处理步骤的节省。

    Semiconductor structures having improved contact resistance
    13.
    发明授权
    Semiconductor structures having improved contact resistance 有权
    具有改善的接触电阻的半导体结构

    公开(公告)号：US08685809B2

    公开(公告)日：2014-04-01

    申请号：US13454709

    申请日：2012-04-24

    Applicant: Bruce B. Doris ,  Carl J. Radens ,  Anthony K. Stamper ,  Jay W. Strane

    Inventor： Bruce B. Doris ,  Carl J. Radens ,  Anthony K. Stamper ,  Jay W. Strane

    IPC: H01L21/336

    CPC classification number: H01L21/28518 ,  B81B2207/07 ,  B81C1/00095 ,  B81C2201/0149 ,  H01L21/3086 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.

    Abstract translation: 自组装聚合物技术用于在存在于半导体结构的导电接触区域中的材料内形成至少一个有序的纳米尺度图案。 具有有序纳米尺寸图案的材料是场效应晶体管的互连结构或半导体源和漏极扩散区的导电材料。 在接触区域内有序的纳米尺寸图案材料的存在增加了用于随后的接触形成的总面积（即界面面积），这又降低了结构的接触电阻。 接触电阻的降低又改善了通过结构的电流的流动。 除了上述之外，本发明的方法和结构不影响结构的结电容，因为结面积保持不变。

    REPLACEMENT GATE MOSFET WITH SELF-ALIGNED DIFFUSION CONTACT
    15.
    发明申请
    REPLACEMENT GATE MOSFET WITH SELF-ALIGNED DIFFUSION CONTACT 有权
    具有自对准扩散接触的更换栅极MOSFET

    公开(公告)号：US20110298017A1

    公开(公告)日：2011-12-08

    申请号：US12795973

    申请日：2010-06-08

    Applicant: Sameer H. Jain ,  Carl J. Radens ,  Shahab Siddiqui ,  Jay W. Strane

    Inventor： Sameer H. Jain ,  Carl J. Radens ,  Shahab Siddiqui ,  Jay W. Strane

    IPC: H01L29/78 ,  H01L21/28

    CPC classification number: H01L29/7833 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659

    Abstract: A replacement gate field effect transistor includes at least one self-aligned contact that overlies a portion of a dielectric gate cap. A replacement gate stack is formed in a cavity formed by removal of a disposable gate stack. The replacement gate stack is subsequently recessed, and a dielectric gate cap having sidewalls that are vertically coincident with outer sidewalls of the gate spacer is formed by filling the recess over the replacement gate stack. An anisotropic etch removes the dielectric material of the planarization layer selective to the material of the dielectric gate cap, thereby forming at least one via cavity having sidewalls that coincide with a portion of the sidewalls of the gate spacer. A portion of each diffusion contact formed by filling the at least one via cavity overlies a portion of the gate spacer and protrudes into the dielectric gate cap.

    Abstract translation: 替代栅极场效应晶体管包括至少一个自对准接触，其覆盖在电介质栅极盖的一部分上。 在通过去除一次性栅极堆叠而形成的空腔中形成替换栅极堆叠。 替换栅极堆叠随后被凹入，并且具有与栅极间隔物的外侧壁垂直重合的侧壁的电介质栅极盖通过在该替代栅极叠层上填充该凹槽来形成。 各向异性蚀刻去除对介电栅极盖的材料有选择性的平坦化层的电介质材料，从而形成具有与栅极间隔物的侧壁的一部分重合的侧壁的至少一个通孔。 通过填充至少一个通孔形成的每个扩散接触部分覆盖在栅极间隔物的一部分上并且突出到电介质栅极帽中。

    Methods for forming high performance gates and structures thereof
    17.
    发明授权
    Methods for forming high performance gates and structures thereof 失效
    形成高性能栅极的方法及其结构

    公开(公告)号：US07790553B2

    公开(公告)日：2010-09-07

    申请号：US12170687

    申请日：2008-07-10

    Applicant: Huilong Zhu ,  Xiaomeng Chen ,  Mahender Kumar ,  Brian J. Greene ,  Bachir Dirahoui ,  Jay W. Strane ,  Gregory G. Freeman

    Inventor： Huilong Zhu ,  Xiaomeng Chen ,  Mahender Kumar ,  Brian J. Greene ,  Bachir Dirahoui ,  Jay W. Strane ,  Gregory G. Freeman

    IPC: H01L21/8234

    CPC classification number: H01L21/823842 ,  H01L21/82385 ,  H01L21/823857

    Abstract: Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.

    Abstract translation: 公开了在MOSFET中形成高性能栅极的方法及其结构。 一个实施例包括提供包括第一短沟道有源区，第二短沟道有源区和长沟道有源区的衬底的方法，每个有源区通过浅沟槽隔离（STI）与另一个分离。 以及在所述长沟道有源区上形成具有多晶硅栅极的场效应晶体管（FET），在所述第一短沟道有源区上具有第一功函数调节材料的第一双金属栅极FET和具有第二双金属栅极FET的第二双金属栅极FET， 第二短通道有源区域上的功函数调整材料，其中第一和第二功函数调节材料不同。

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