Individual I/O modulation in memory devices
    11.
    发明申请
    Individual I/O modulation in memory devices 失效
    存储设备中的单独I / O调制

    公开(公告)号:US20050169068A1

    公开(公告)日:2005-08-04

    申请号:US10766004

    申请日:2004-01-29

    CPC classification number: G11C7/08

    Abstract: A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.

    Abstract translation: 一种具有降低功耗的DRAM电路,在某些情况下,存储器阵列存取速度更快。 与阈值电容/长度相比,根据其电容/长度来感测连接到存储器阵列的输入/输出线。 比阈值更短或更低电容性的输入/输出线比比阈值更长,更容性的输入/输出线被感测得更早。 由于更短的输入/输出线路被更快地感测到,所以它们需要更少的功率并且可以更快地访问。

    Ammunition feeder
    12.
    发明申请
    Ammunition feeder 失效
    弹药进料器

    公开(公告)号:US20050081420A1

    公开(公告)日:2005-04-21

    申请号:US10672594

    申请日:2003-09-27

    Applicant: Jeffrey Wright

    Inventor: Jeffrey Wright

    CPC classification number: F42B39/08

    Abstract: Ammunition feeder with a handle portion and a head portion. The handle portion is integrally attached to the head portion. The handle portion is a flat elongate shape having raised portions to help the user maintain his grip on the handle. The head portion is shaped to accept the front end of a standard ammunition belt. The head is flattened longitudinally on one side and includes a longitudinal recess so that the feed pawl on a standard machine gun is not activated by the head. A preferred embodiment includes that the feeder fits with the M 60 machine gun and the 240 Golf machine gun.

    Abstract translation: 具有把手部分和头部的弹药进料器。 手柄部分一体地附接到头部。 手柄部分是具有凸起部分的平坦的细长形状,以帮助使用者保持对手柄的握持。 头部被成形为接受标准弹药带的前端。 头部在一侧纵向扁平化并且包括纵向凹槽,使得标准机枪上的进给爪不被头部激活。 一个优选实施例包括进料器与M 60机枪和240高尔夫机枪配合。

    METHOD FOR WRITING TO MULTIPLE BANKS OF A MEMORY DEVICE
    15.
    发明申请
    METHOD FOR WRITING TO MULTIPLE BANKS OF A MEMORY DEVICE 失效
    用于写入存储器件的多个银行的方法

    公开(公告)号:US20070286002A1

    公开(公告)日:2007-12-13

    申请号:US11841814

    申请日:2007-08-20

    Abstract: In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.

    Abstract translation: 在诸如同步动态随机存取存储器(SDRAM)的多存储体存储器系统中,提供了将数据写入存储体的方法。 这种方法允许写入任意数量的银行。 更具体地说,这种方法允许写入一个和所有银行之间的选定数量的银行。 此外,该方法通过允许每个存储体中的任何行被访问而保留所选存储体的离散性质,而不管其他存储体中激活的行如何。 因此,为了将数据写入测试和非测试模式的目的,可以同时访问旨在存储类似数据的不同存储体的行。 这允许更快地写入SDRAM,而不会由其他快速写入模式(如数据压缩)创建的错误。

    System and method for providing temperature data from a memory device having a temperature sensor
    16.
    发明申请
    System and method for providing temperature data from a memory device having a temperature sensor 失效
    用于从具有温度传感器的存储器件提供温度数据的系统和方法

    公开(公告)号:US20070140315A1

    公开(公告)日:2007-06-21

    申请号:US11303680

    申请日:2005-12-16

    CPC classification number: G01K7/00 G01K2219/00

    Abstract: A circuit and method for providing temperature data indicative of a temperature measured by a temperature sensor. The circuit is coupled to the temperature sensor and configured to identify for a coarse temperature range one of a plurality of fine temperature ranges corresponding to the temperature measured by the temperature sensor and generate temperature data that is provided on an asynchronous output data path.

    Abstract translation: 一种用于提供表示由温度传感器测量的温度的温度数据的电路和方法。 电路耦合到温度传感器并且被配置为识别对应于由温度传感器测量的温度的多个精细温度范围之一的粗略温度范围,并且生成提供在异步输出数据路径上的温度数据。

    Memory array decoder
    17.
    发明申请
    Memory array decoder 有权
    存储器阵列解码器

    公开(公告)号:US20070121416A1

    公开(公告)日:2007-05-31

    申请号:US11698467

    申请日:2007-01-26

    CPC classification number: G11C8/10 G11C11/4087 G11C29/844

    Abstract: An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein the decoder is operable to generate a location select signal for selecting a first location, the decoder being responsive to the pre-decoded location address signal, and wherein the redundant decoder is operable to generate a redundant location select signal for selecting a second location, the redundant decoder being responsive to the redundant location address enable signal, and terminating one of the generation of a location select signal and the generation of a redundant location select signal in response to a precharge signal.

    Abstract translation: 一种用于选择存储设备中的存储位置的装置和方法,包括接收预解码位置地址信号,匹配信号和冗余位置地址使能信号中的至少一个,使解码器和冗余解码器之一响应 其中所述解码器可操作以产生用于选择第一位置的位置选择信号,所述解码器响应于所述预解码的位置地址信号,并且其中所述冗余解码器可操作以产生用于 选择第二位置,所述冗余解码器响应于所述冗余位置地址使能信号,并且终止所述产生位置选择信号和响应于预充电信号产生冗余位置选择信号。

    System and method for decoding commands based on command signals and operating state
    18.
    发明申请
    System and method for decoding commands based on command signals and operating state 有权
    基于命令信号和操作状态对命令进行解码的系统和方法

    公开(公告)号:US20060265556A1

    公开(公告)日:2006-11-23

    申请号:US11121868

    申请日:2005-05-03

    Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

    Abstract translation: 一种用于对命令信号进行解码的系统和方法,该系统和方法包括一个命令解码器,该命令解码器经配置以产​​生内部控制信号,以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时,根据命令信号从第一组操作中选择命令,并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。

    Reclosable carton
    19.
    发明申请
    Reclosable carton 审中-公开
    可重新封闭的纸箱

    公开(公告)号:US20060255107A1

    公开(公告)日:2006-11-16

    申请号:US11432921

    申请日:2006-05-12

    Applicant: Jeffrey Wright

    Inventor: Jeffrey Wright

    Abstract: A carton accommodates a flexible vessel and includes a reclosure feature. The reclosure feature provides a relatively tight seal for the contents of the flexible vessel.

    Abstract translation: 纸箱容纳柔性容器并包括重合闸功能。 重新闭合特征为柔性容器的内容物提供相对紧密的密封。

    Memory architecture
    20.
    发明申请
    Memory architecture 有权
    内存架构

    公开(公告)号:US20060245231A1

    公开(公告)日:2006-11-02

    申请号:US11476744

    申请日:2006-06-29

    Abstract: A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays. The unidirectional row logic is located in the outward periphery of its associated array, but is not within a throat region between two arrays. The location of the row logic allows the throat region to include more bidirectional IO circuitry and signal lines servicing two arrays, which increases the performance of the SDRAM. In addition, separate power bussing is employed for the memory arrays and IO circuitry. This prevents noise from the arrays from affecting the IO circuitry and signal lines of the throat region and vice versa.

    Abstract translation: DDR SDRAM,其中单向行逻辑与单个存储器阵列相关联并连接到单个存储器阵列,而不是与多个存储器阵列相关联并连接到多个存储器阵列。 单向行逻辑位于其关联阵列的外围,但不在两个阵列之间的喉部区域内。 行逻辑的位置允许喉部区域包括更多的双向IO电路和服务两个阵列的信号线,这增加了SDRAM的性能。 此外,存储器阵列和IO电路采用单独的功率总线。 这可以防止阵列的噪声影响喉部区域的IO电路和信号线,反之亦然。

Patent Agency Ranking