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29 条记录 (耗时 0.021 秒)

    Semiconductor device
    17.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06924516B2

    公开(公告)日：2005-08-02

    申请号：US10711134

    申请日：2004-08-26

    申请人： Kaoru Inoue ,  Katsunori Nishii ,  Hiroyuki Masato

    发明人： Kaoru Inoue ,  Katsunori Nishii ,  Hiroyuki Masato

    IPC分类号： H01L29/04 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778 ,  H01L31/0328

    CPC分类号： H01L29/7783 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/42316

    摘要： A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer,wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.

    摘要翻译： 半导体器件包括：衬底; 包括形成在衬底上的GaN的缓冲层，其中：缓冲层的表面是Ga原子的c个面; 在缓冲层上形成包括GaN或InGaN的沟道层，其中：沟道层的表面是Ga或In原子的c面; 包括形成在沟道层上的AlGaN的电子给体层，其中：电子给体层的表面是Al或Ga原子的c个面; 形成在电子供体层上的源电极和漏电极; 形成在源电极和漏电极之间的包含GaN或InGaAlN的覆盖层，其中：覆盖层的表面是Ga或In原子的c面，并且覆盖层的至少一部分与电子给体层接触; 以及形成为至少一部分与盖层接触的栅电极。

    GaN-based HFET having a surface-leakage reducing cap layer
    18.
    发明授权
    GaN-based HFET having a surface-leakage reducing cap layer 有权
    具有表面泄漏降低帽层的GaN基HFET

    公开(公告)号：US06639255B2

    公开(公告)日：2003-10-28

    申请号：US09733593

    申请日：2000-12-08

    申请人： Kaoru Inoue ,  Katsunori Nishii ,  Hiroyuki Masato

    发明人： Kaoru Inoue ,  Katsunori Nishii ,  Hiroyuki Masato

    IPC分类号： H01L29737

    CPC分类号： H01L29/7783 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/42316

    摘要： A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer, wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.

    摘要翻译： 半导体器件包括：衬底; 包括形成在衬底上的GaN的缓冲层，其中：缓冲层的表面是Ga原子的c个面; 在缓冲层上形成包括GaN或InGaN的沟道层，其中：沟道层的表面是Ga或In原子的c面; 包括形成在沟道层上的AlGaN的电子给体层，其中：电子给体层的表面是Al或Ga原子的c个面; 形成在电子供体层上的源电极和漏电极; 形成在源电极和漏电极之间的包含GaN或InGaAlN的覆盖层，其中：所述覆盖层的表面是Ga或In原子的c面，并且所述覆盖层的至少一部分与所述电子给体层接触; 以及形成为至少一部分与盖层接触的栅电极。

    Method of manufacturing semiconductor device
    19.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US6153499A

    公开(公告)日：2000-11-28

    申请号：US289946

    申请日：1999-04-13

    申请人： Yoshiharu Anda ,  Toshinobu Matsuno ,  Katsunori Nishii ,  Kaoru Inoue ,  Manabu Yanagihara ,  Mitsuru Tanabe

    发明人： Yoshiharu Anda ,  Toshinobu Matsuno ,  Katsunori Nishii ,  Kaoru Inoue ,  Manabu Yanagihara ,  Mitsuru Tanabe

    IPC分类号： H01L21/28 ,  H01L21/027 ,  H01L21/285 ,  H01L21/338 ,  H01L21/768 ,  H01L29/812 ,  H01L21/44

    CPC分类号： H01L21/28581 ,  H01L21/0271 ,  H01L21/0277 ,  H01L21/76816 ,  Y10S438/949

    摘要： A first resist film for EB exposure, a buffer film, and a second resist film for i-line exposure are applied sequentially onto a substrate. Thereafter, the second resist film and the buffer film are subjected to patterning for forming a first opening. Then, dry etching is performed with respect to the first resist film masked with the second resist film to transfer the pattern of the second resist film to the first resist film and thereby form a second opening in the first resist film. Subsequently, a third resist film of chemically amplified type is applied to the entire surface of the first resist film to form a mixing layer in conjunction with the first resist film. As a result, the wall faces of the second opening are covered with the mixing layer and the width of the second opening is thereby reduced.

    摘要翻译： 用于EB曝光的第一抗蚀剂膜，缓冲膜和用于i线曝光的第二抗蚀剂膜顺序地施加到基板上。 此后，对第二抗蚀剂膜和缓冲膜进行用于形成第一开口的图案化。 然后，相对于用第二抗蚀剂膜掩蔽的第一抗蚀剂膜进行干蚀刻，将第二抗蚀剂膜的图案转印到第一抗蚀剂膜上，从而在第一抗蚀剂膜中形成第二开口。 随后，将化学放大型的第三抗蚀剂膜施加到第一抗蚀剂膜的整个表面上以与第一抗蚀剂膜结合形成混合层。 结果，第二开口的壁面被混合层覆盖，从而减小了第二开口的宽度。

    Field-effect transistor and method of manufacturing the same
    20.
    发明授权
    Field-effect transistor and method of manufacturing the same 失效
    场效应晶体管及其制造方法

    公开(公告)号：US5585655A

    公开(公告)日：1996-12-17

    申请号：US517435

    申请日：1995-08-21

    申请人： Yorito Ota ,  Katsunori Nishii ,  Mitsuru Nishitsuji ,  Hiroyuki Masato ,  Hiromasa Fujimoto

    发明人： Yorito Ota ,  Katsunori Nishii ,  Mitsuru Nishitsuji ,  Hiroyuki Masato ,  Hiromasa Fujimoto

    IPC分类号： H01L21/335 ,  H01L29/10 ,  H01L29/47 ,  H01L29/812 ,  H01L29/80

    CPC分类号： H01L29/66462 ,  H01L29/1029 ,  H01L29/475 ,  H01L29/8128

    摘要： On a semi-insulating substrate is formed a conductive layer and an undoped layer. On specified regions of the conductive layer are formed ohmic electrodes, each serving as a source electrode or a drain electrode, via a pair of square contact regions. The circumferential edges of the contact regions are undercut beneath the ohmic electrodes. Between the pair of contact regions on the conductive layer is formed a gate electrode by self alignment using the ohmic electrodes as a mask. The gate electrode has extended in the direction of gate width and the extended portion serves as a withdrawn portion of the gate electrode. Upper electrodes are formed by self alignment in the same process in which the gate electrode is formed.

    摘要翻译： 在半绝缘基板上形成导电层和未掺杂层。 在导电层的指定区域上形成欧姆电极，每个电极用作源电极或漏电极，经由一对正方形接触区域。 接触区域的圆周边缘在欧姆电极之下被切下。 通过使用欧姆电极作为掩模的自对准，在导电层上的一对接触区域之间形成栅电极。 栅电极在栅极宽度方向上延伸，并且延伸部分用作栅电极的退出部分。 上电极通过在其中形成栅电极的相同工艺中的自对准形成。