公开(公告)号：US20110300823A1

公开(公告)日：2011-12-08

申请号：US12673323

申请日：2007-10-02

Applicant: Kenji Kawakami ,  Masaomi Tsuru ,  Hiroyuki Mizutani ,  Yusuke Kitsukawa

Inventor： Kenji Kawakami ,  Masaomi Tsuru ,  Hiroyuki Mizutani ,  Yusuke Kitsukawa

IPC: H04B1/26

CPC classification number: H03D7/165 ,  H03D2200/0082

Abstract: An image rejection mixer and a communication device, which may suppress unwanted frequency components of a high power output assuming a fourth-order harmonic mixer. The image rejection mixer and communication device include first and second fourth-order harmonic mixers, a 90-degree IF synthesis distributor, a 90-degree LO distributor, and a 90-degree RF synthesis distributor. Use of the 90-degree distributors for LO distribution of the fourth-order harmonic image rejection mixer suppresses the unwanted frequency components of the high power output.

Abstract translation: 图像抑制混频器和通信设备，其可以抑制假设四阶谐波混频器的高功率输出的不期望的频率分量。 镜像抑制混频器和通信装置包括第一和第二四阶谐波混频器，90度IF合成分配器，90度LO分配器和90度RF合成分配器。 使用90度分配器进行四阶谐波抑制混频器的LO分配抑制高功率输出的不需要的频率分量。

公开(公告)号：US08062911B2

公开(公告)日：2011-11-22

申请号：US11958369

申请日：2007-12-17

Applicant: Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

Inventor： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

IPC: H01L21/66 ,  G01R31/26

CPC classification number: G01R3/00 ,  G01R1/07342

Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.

Abstract translation: 通过选择性地在晶片的主表面上沉积在要形成金属膜的区域中的铜膜和当探针卡是在粘合环外部时将在粘合环外部的区域，制造具有足够高度的探针 制造的 形成金属膜，聚酰亚胺膜，互连，另一聚酰亚胺膜，另一互连和另外的聚酰亚胺膜; 然后取出晶片和铜膜。 根据本发明，在利用半导体集成电路器件的制造技术的情况下，使用具有以上述方式形成的探针的探测器（薄膜探针）进行探针测试时，可以防止探测器的破损， 待测试的晶圆。

公开(公告)号：US08018290B2

公开(公告)日：2011-09-13

申请号：US12439764

申请日：2007-10-15

Applicant: Hiroyuki Mizutani ,  Kazuhiro Nishida ,  Masaomi Tsuru ,  Kenji Kawakami ,  Morishige Hieda ,  Moriyasu Miyazaki

Inventor： Hiroyuki Mizutani ,  Kazuhiro Nishida ,  Masaomi Tsuru ,  Kenji Kawakami ,  Morishige Hieda ,  Moriyasu Miyazaki

IPC: H03B25/00

CPC classification number: H03B5/1847 ,  G01S7/35

Abstract: An output terminal 6 is provided at the connecting point 5 between the collector terminal of a transistor 1 and an open-ended stub 4 by connecting the open-ended stub 4 to the collector terminal of the transistor 1, the open-ended stub 4 having a line length equal to a quarter of the wavelength of a signal of frequency 2N·F0 or 2N times the oscillation frequency F0. In addition, an output terminal 9 is provided at a connecting point 8 located at a distance equal to a quarter of the wavelength of a signal of oscillation frequency F0 from the end of an open-ended stub 7 by connecting the open-ended stub 7 to the base terminal of the transistor 1, the open-ended stub 7 having a line length longer than a quarter of the wavelength of the signal of oscillation frequency F0.

Abstract translation: 通过将开路端子4连接到晶体管1的集电极端子，在晶体管1的集电极端子与开路短截线端子4之间的连接点5处设置有输出端子6，开路短路端子4具有 线长度等于频率为2N·F0或振荡频率F0的2N倍的信号波长的四分之一。 此外，输出端子9设置在连接点8处，该连接点8通过连接开放端短截线7而设置在距离开放端短截线7的端部等于振荡频率F0的信号的波长的四分之一的距离处 到晶体管1的基极，具有比振荡频率F0的信号的波长的四分之一长的线路长度的开路短截线7。

公开(公告)号：US08012287B2

公开(公告)日：2011-09-06

申请号：US12559589

申请日：2009-09-15

Applicant: Kazuhiro Isebo ,  Norio Sakai ,  Kenji Kawakami ,  Nobuaki Ogawa

Inventor： Kazuhiro Isebo ,  Norio Sakai ,  Kenji Kawakami ,  Nobuaki Ogawa

IPC: B32B15/00

CPC classification number: H05K3/4061 ,  G03G15/224 ,  G03G15/225 ,  G03G15/6585 ,  G03G15/6591 ,  H05K1/0306 ,  H05K3/1266 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2203/0143 ,  H05K2203/0156 ,  H05K2203/0517 ,  H05K2203/1189 ,  H05K2203/1545 ,  Y10T29/5313 ,  Y10T29/5317 ,  Y10T156/10 ,  Y10T156/109

Abstract: A via hole forming method and a multilayered board manufacturing method improve manufacturing yield by reducing the required processes. The via hole forming method includes a first step of forming a toner image by attaching toner particles, containing a conductive material and having a protruding portion, onto the surface of a first photosensitive member so that the protruding portion is directed to the outside; and a second step of opposing the surface of the first photosensitive member to one principal surface of a green sheet containing an insulating material and transferring the toner image to the one principal surface of the green sheet so that the protruding portions of the toner particles protrude into the green sheet so as to reach the other principal surface of the green sheet and the toner particles are buried in the green sheet. The via holes are formed using an electrophotographic printing method.

Abstract translation: 通孔形成方法和多层板制造方法通过减少所需的工艺来提高制造成品率。 通孔形成方法包括：第一步骤，通过将包含导电材料并具有突出部分的调色剂颗粒附着到第一感光构件的表面上以使得突出部分被引导到外部来形成调色剂图像; 以及将第一感光构件的表面相对于包含绝缘材料的生片的一个主表面并将调色剂图像转印到生片的一个主表面的第二步骤，使得调色剂颗粒的突出部分突出到 生片从而到达生片的另一个主表面和调色剂颗粒被埋在生片中。 通孔使用电子照相印刷法形成。

公开(公告)号：US20100301884A1

公开(公告)日：2010-12-02

申请号：US12787869

申请日：2010-05-26

Applicant: Etsuko Takane ,  Yasunori Narizuka ,  Akira Yabushita ,  Kenji Kawakami ,  Akio Hasebe

Inventor： Etsuko Takane ,  Yasunori Narizuka ,  Akira Yabushita ,  Kenji Kawakami ,  Akio Hasebe

IPC: G01R31/02 ,  H01R13/02 ,  H01R43/00

CPC classification number: H05K3/4007 ,  G01R1/06733 ,  G01R1/0735 ,  G01R3/00 ,  H05K3/06 ,  H05K3/205 ,  H05K2201/0367 ,  H05K2201/09845 ,  H05K2203/0574 ,  Y10T29/49224

Abstract: A semiconductor chip inspection apparatus largely reduces occurrence of damage due to foreign matter in an inspection process and improves durability at the same time of miniaturization is provided. As to a highly accurate thin-film probe sheet which performs: a contact to electrode pads arranged at a narrow pitch and a high density along with integration of semiconductor chip; and an inspection of semiconductor chips, by providing two layers of metal films selectively removable in a step-like shape in a periphery region of fine contact terminal having sharp tips and arranged at a high density and a narrow pitch at the same level as electrode pads, an upper periphery of the contact terminals is covered with an insulating film, and a large space region is formed.

Abstract translation: 半导体芯片检查装置大大减少了检查过程中由于异物引起的损坏的发生，并提供了同时小型化的耐久性。 对于高精度的薄膜探针片，其执行：与半导体芯片的集成一起以窄间距和高密度布置的电极焊盘的接触; 以及对半导体芯片的检查，通过在具有尖锐尖端的精细接触端子的周边区域中提供两级可选择性地以阶梯状形式移除的金属膜，并以与电极焊盘相同的高度密度和窄间距排列 接触端子的上周边被绝缘膜覆盖，形成大的空间区域。

公开(公告)号：US07675383B2

公开(公告)日：2010-03-09

申请号：US11795335

申请日：2005-01-27

Applicant: Masatake Hangai ,  Tamotsu Nishino ,  Shinnosuke Soda ,  Kenichi Miyaguchi ,  Kenji Kawakami ,  Masaomi Tsuru ,  Satoshi Hamano ,  Moriyasu Miyazaki ,  Tadashi Takagi

Inventor： Masatake Hangai ,  Tamotsu Nishino ,  Shinnosuke Soda ,  Kenichi Miyaguchi ,  Kenji Kawakami ,  Masaomi Tsuru ,  Satoshi Hamano ,  Moriyasu Miyazaki ,  Tadashi Takagi

IPC: H01P1/10 ,  H01H9/54

CPC classification number: H01H59/0009 ,  H01H9/54 ,  H01P1/127 ,  H01P1/15

Abstract: A switch circuit includes: a first input and output terminal; a first inductor connected with the first input and output terminal; a capacitor connected with the first inductor; a second input and output terminal connected with the capacitor; a first MEMS switch connected with one end of the capacitor; a second MEMS switch connected with the other end of the capacitor; and a second inductor connected between the first MEMS switch and the second MEMS switch, and satisfies a relationship of f=1/(2π√CL1)=1/(2π√CL2), where L1 is an inductance of the first inductor, L2 is an inductance of the second inductor, C is a capacitance of the capacitor, and f is a use frequency.

Abstract translation: 一种开关电路包括：第一输入和输出端; 与第一输入和输出端连接的第一电感器; 与第一电感器连接的电容器; 与电容器连接的第二输入和输出端子; 与电容器的一端连接的第一MEMS开关; 与电容器的另一端连接的第二MEMS开关; 以及连接在第一MEMS开关和第二MEMS开关之间的第二电感器，并且满足f = 1 /（2＆pgr;√CL1）= 1 /（2＆pgr;√CL2）的关系，其中L1是第一电感器的电感 ，L2是第二电感器的电感，C是电容器的电容，f是使用频率。

公开(公告)号：US07675376B2

公开(公告)日：2010-03-09

申请号：US11629531

申请日：2005-03-07

Applicant: Masaomi Tsuru ,  Kenji Kawakami ,  Kenichi Tajima ,  Moriyasu Miyazaki ,  Kazuhiro Miyamoto ,  Masafumi Nakane

Inventor： Masaomi Tsuru ,  Kenji Kawakami ,  Kenichi Tajima ,  Moriyasu Miyazaki ,  Kazuhiro Miyamoto ,  Masafumi Nakane

IPC: H03B5/18

CPC classification number: H03H11/44 ,  H03B5/1203 ,  H03B5/1228 ,  H03B5/1231 ,  H03B5/1243 ,  H03B5/1293 ,  H03B2200/0042 ,  H03H11/28 ,  H03H11/481

Abstract: A voltage-controlled oscillator has a tuned circuit for controlling the oscillation frequency. The tuned circuit has a variable-capacitance element whose capacitance varies in response to a control voltage and a negative capacitance circuit whose impedance frequency characteristics have opposite characteristics to those of a normal capacitance, and which is connected to the variable-capacitance element. The configuration enables increasing the variation ratio corresponding to the control voltage of the combined capacitance composed of the variable-capacitance element and negative capacitance circuit, thereby broadening the oscillation frequency band.

Abstract translation: 压控振荡器具有用于控制振荡频率的调谐电路。 调谐电路具有可变电容元件，其电容响应于阻抗频率特性与正常电容具有相反特性的控制电压和负电容电路而变化，并且连接到可变电容元件。 该配置能够增加与由可变电容元件和负电容电路组成的组合电容的控制电压相对应的变化率，从而使振荡频带变宽。

公开(公告)号：US20090320986A1

公开(公告)日：2009-12-31

申请号：US12559589

申请日：2009-09-15

Applicant: Kazuhiro ISEBO ,  Norio SAKAI ,  Kenji KAWAKAMI ,  Nobuaki OGAWA

Inventor： Kazuhiro ISEBO ,  Norio SAKAI ,  Kenji KAWAKAMI ,  Nobuaki OGAWA

IPC: B32B37/02 ,  G03G13/16 ,  G03G13/20

CPC classification number: H05K3/4061 ,  G03G15/224 ,  G03G15/225 ,  G03G15/6585 ,  G03G15/6591 ,  H05K1/0306 ,  H05K3/1266 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2203/0143 ,  H05K2203/0156 ,  H05K2203/0517 ,  H05K2203/1189 ,  H05K2203/1545 ,  Y10T29/5313 ,  Y10T29/5317 ,  Y10T156/10 ,  Y10T156/109

Abstract: A via hole forming method and a multilayered board manufacturing method improve manufacturing yield by reducing the required processes. The via hole forming method includes a first step of forming a toner image by attaching toner particles, containing a conductive material and having a protruding portion, onto the surface of a first photosensitive member so that the protruding portion is directed to the outside; and a second step of opposing the surface of the first photosensitive member to one principal surface of a green sheet containing an insulating material and transferring the toner image to the one principal surface of the green sheet so that the protruding portions of the toner particles protrude into the green sheet so as to reach the other principal surface of the green sheet and the toner particles are buried in the green sheet. The via holes are formed using an electrophotographic printing method.

Abstract translation: 通孔形成方法和多层板制造方法通过减少所需的工艺来提高制造成品率。 通孔形成方法包括：第一步骤，通过将包含导电材料并具有突出部分的调色剂颗粒附着到第一感光构件的表面上以使得突出部分被引导到外部来形成调色剂图像; 以及将第一感光构件的表面相对于包含绝缘材料的生片的一个主表面并将调色剂图像转印到生片的一个主表面的第二步骤，使得调色剂颗粒的突出部分突出到 生片从而到达生片的另一个主表面和调色剂颗粒被埋在生片中。 通孔使用电子照相印刷法形成。

公开(公告)号：US20080136557A1

公开(公告)日：2008-06-12

申请号：US11795335

申请日：2005-01-27

Applicant: Masatake Hangai ,  Tamotsu Nishino ,  Shinnosuke Soda ,  Kenichi Miyaguchi ,  Kenji Kawakami ,  Masaomi Tsuru ,  Satoshi Hamano ,  Moriyasu Miyazaki ,  Tadashi Takagi

Inventor： Masatake Hangai ,  Tamotsu Nishino ,  Shinnosuke Soda ,  Kenichi Miyaguchi ,  Kenji Kawakami ,  Masaomi Tsuru ,  Satoshi Hamano ,  Moriyasu Miyazaki ,  Tadashi Takagi

IPC: H03H7/01

CPC classification number: H01H59/0009 ,  H01H9/54 ,  H01P1/127 ,  H01P1/15

Abstract: A switch circuit includes: a first input and output terminal; a first inductor connected with the first input and output terminal; a capacitor connected with the first inductor; a second input and output terminal connected with the capacitor; a first MEMS switch connected with one end of the capacitor; a second MEMS switch connected with the other end of the capacitor; and a second inductor connected between the first MEMS switch and the second MEMS switch, and satisfies a relationship of f=1/(2π√CL1)=1/(2π√CL2), where L1 is an inductance of the first inductor, L2 is an inductance of the second inductor, C is a capacitance of the capacitor, and f is a use frequency.

Abstract translation: 一种开关电路包括：第一输入和输出端; 与第一输入和输出端连接的第一电感器; 与第一电感器连接的电容器; 与电容器连接的第二输入和输出端子; 与电容器的一端连接的第一MEMS开关; 与电容器的另一端连接的第二MEMS开关; 以及连接在第一MEMS开关和第二MEMS开关之间的第二电感器，并且满足f = 1 /（2π√CL1/2）= 1 /（2π√CL< / SUB>），其中L 1是第一电感器的电感，L 2是第二电感器的电感，C是电容器的电容，f 是使用频率。

公开(公告)号：US07018857B2

公开(公告)日：2006-03-28

申请号：US10459598

申请日：2003-06-12

Applicant: Masatoshi Kanamaru ,  Takanori Aono ,  Tatsuya Nagata ,  Kenji Kawakami ,  Hideyuki Aoki

Inventor： Masatoshi Kanamaru ,  Takanori Aono ,  Tatsuya Nagata ,  Kenji Kawakami ,  Hideyuki Aoki

IPC: H01L21/66

CPC classification number: G01R1/06761 ,  G01R1/0735 ,  G01R3/00

Abstract: A manufacturing method for improving the yield in a semiconductor manufacturing process and reducing the manufacturing cost produces a semiconductor device that is inexpensively manufactured and has a high reliability by reliably making contact during inspection with a suitable pressing force, while limiting damage to an electrode pad even when many inspected electrodes are inspected. A substrate used for inspection of the semiconductor device has a beam, a probe on the beam having a projecting shape for coming in contact with an electrode (electrode pad) of the semiconductor device, and a secondary electrode electrically connected to the probe through an electrically conductive member disposed on the side of the beam opposed to the side where the probe is provided. In an inspecting process, an inspecting device having a layer having many projections formed in the probe come in contact with the electrode pad of the semiconductor device.

Abstract translation: 一种用于提高半导体制造工艺中的产量并降低制造成本的制造方法产生了廉价制造的半导体器件，并且通过在合适的按压力期间可靠地进行接触检查而具有高的可靠性，同时限制对电极焊盘的损伤甚至 当检查了许多检查电极时。 用于检查半导体器件的衬底具有光束，所述光束上的探针具有用于与半导体器件的电极（电极焊盘）接触的突出形状，以及通过电气电连接到探针的次级电极 导电构件设置在与设置探针的一侧相对的梁的侧面上。 在检查过程中，具有形成在探针中的具有许多突起的层的检查装置与半导体器件的电极焊盘接触。