公开(公告)号：US20060043593A1

公开(公告)日：2006-03-02

申请号：US11184980

申请日：2005-07-20

申请人： Terutaka Mori ,  Yasunori Narizuka ,  Akira Yabushita ,  Etsuko Takane ,  Akio Hasebe ,  Kenji Kawakami

发明人： Terutaka Mori ,  Yasunori Narizuka ,  Akira Yabushita ,  Etsuko Takane ,  Akio Hasebe ,  Kenji Kawakami

IPC分类号： H01L23/52

CPC分类号： G01R1/06711 ,  G01R1/06744 ,  G01R1/0735 ,  G01R3/00

摘要： In the connecting apparatus for inspecting the semiconductor chip, in which contact terminals are electrically connected to each of the plurality of electrode pads formed on the semiconductor chips, a part of metal projections in the shape of quadrangular pyramid which constitute the contact terminals is composed of insulator in the present invention. Therefore, the inspection of semiconductor chips performed by simultaneously transmitting high-speed signals to the plurality of minute electrode pads arranged at a narrow pitch on the semiconductor chips can be realized.

摘要翻译： 在用于检查半导体芯片的连接装置中，其中接触端子电连接到形成在半导体芯片上的多个电极焊盘中的每一个，构成接触端子的四角锥形状的金属突起的一部分由 绝缘体。 因此，可以实现通过同时向半导体芯片上以窄间距布置的多个微小电极焊盘传输高速信号而执行的半导体芯片的检查。

公开(公告)号：US20110014727A1

公开(公告)日：2011-01-20

申请号：US12883982

申请日：2010-09-16

申请人： Akira YABUSHITA ,  Yasunori Narizuka ,  Susumu Kasukabe ,  Terutaka Mori ,  Etsuko Takane ,  Akio Hasebe ,  Kenji Kawakami

发明人： Akira YABUSHITA ,  Yasunori Narizuka ,  Susumu Kasukabe ,  Terutaka Mori ,  Etsuko Takane ,  Akio Hasebe ,  Kenji Kawakami

IPC分类号： H01L21/66 ,  H05K3/02

CPC分类号： G01R1/0735 ,  Y10T29/49156

摘要： In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided.

摘要翻译： 在用于与由半导体芯片的集成度增加和半导体芯片的检查而产生的窄间距高密度设置的电极焊盘接触的高精度薄膜探针片中，其中金属 在具有尖锐尖端的微小接触端子周围的周边区域中预先形成相对于端子金属可选择的膜，并以与电极焊盘相同的窄间距高密度地设置。 因此，检查过程中的损坏的发生显着减少，并且可以提供同时实现小型化和耐久性的检查装置。

公开(公告)号：US20060094162A1

公开(公告)日：2006-05-04

申请号：US11253575

申请日：2005-10-20

申请人： Akira Yabushita ,  Yasunori Narizuka ,  Susumu Kasukabe ,  Terutaka Mori ,  Etsuko Takane ,  Akio Hasebe ,  Kenji Kawakami

发明人： Akira Yabushita ,  Yasunori Narizuka ,  Susumu Kasukabe ,  Terutaka Mori ,  Etsuko Takane ,  Akio Hasebe ,  Kenji Kawakami

IPC分类号： H01L21/50

CPC分类号： G01R1/0735 ,  Y10T29/49156

摘要： In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided.

摘要翻译： 在用于与由半导体芯片的集成度增加和半导体芯片的检查而产生的窄间距高密度设置的电极焊盘接触的高精度薄膜探针片中，其中金属 在具有尖锐尖端的微小接触端子周围的周边区域中预先形成相对于端子金属可选择的膜，并以与电极焊盘相同的窄间距高密度地设置。 因此，检查过程中的损坏的发生显着减少，并且可以提供同时实现小型化和耐久性的检查装置。

公开(公告)号：US20100301884A1

公开(公告)日：2010-12-02

申请号：US12787869

申请日：2010-05-26

申请人： Etsuko Takane ,  Yasunori Narizuka ,  Akira Yabushita ,  Kenji Kawakami ,  Akio Hasebe

发明人： Etsuko Takane ,  Yasunori Narizuka ,  Akira Yabushita ,  Kenji Kawakami ,  Akio Hasebe

IPC分类号： G01R31/02 ,  H01R13/02 ,  H01R43/00

CPC分类号： H05K3/4007 ,  G01R1/06733 ,  G01R1/0735 ,  G01R3/00 ,  H05K3/06 ,  H05K3/205 ,  H05K2201/0367 ,  H05K2201/09845 ,  H05K2203/0574 ,  Y10T29/49224

摘要： A semiconductor chip inspection apparatus largely reduces occurrence of damage due to foreign matter in an inspection process and improves durability at the same time of miniaturization is provided. As to a highly accurate thin-film probe sheet which performs: a contact to electrode pads arranged at a narrow pitch and a high density along with integration of semiconductor chip; and an inspection of semiconductor chips, by providing two layers of metal films selectively removable in a step-like shape in a periphery region of fine contact terminal having sharp tips and arranged at a high density and a narrow pitch at the same level as electrode pads, an upper periphery of the contact terminals is covered with an insulating film, and a large space region is formed.

摘要翻译： 半导体芯片检查装置大大减少了检查过程中由于异物引起的损坏的发生，并提供了同时小型化的耐久性。 对于高精度的薄膜探针片，其执行：与半导体芯片的集成一起以窄间距和高密度布置的电极焊盘的接触; 以及对半导体芯片的检查，通过在具有尖锐尖端的精细接触端子的周边区域中提供两级可选择性地以阶梯状形式移除的金属膜，并以与电极焊盘相同的高度密度和窄间距排列 接触端子的上周边被绝缘膜覆盖，形成大的空间区域。

公开(公告)号：US20100279502A1

公开(公告)日：2010-11-04

申请号：US12836580

申请日：2010-07-15

申请人： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

发明人： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

IPC分类号： H01L21/768

CPC分类号： G01R3/00 ,  G01R1/07342

摘要： A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.

摘要翻译： 通过选择性地在晶片的主表面上沉积在要形成金属膜的区域中的铜膜和当探针卡是在粘合环外部时将在粘合环外部的区域，制造具有足够高度的探针 制造的 形成金属膜，聚酰亚胺膜，互连，另一聚酰亚胺膜，另一互连和另外的聚酰亚胺膜; 然后取出晶片和铜膜。 根据本发明，在利用半导体集成电路器件的制造技术的情况下，使用具有以上述方式形成的探针的探测器（薄膜探针）进行探针测试时，可以防止探测器的破损， 待测试的晶圆。

公开(公告)号：US08206997B2

公开(公告)日：2012-06-26

申请号：US12836580

申请日：2010-07-15

申请人： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

发明人： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G01R3/00 ,  G01R1/07342

摘要： A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.

摘要翻译： 通过选择性地在晶片的主表面上沉积在要形成金属膜的区域中的铜膜和当探针卡是在粘合环外部时将在粘合环外部的区域，制造具有足够高度的探针 制造的 形成金属膜，聚酰亚胺膜，互连，另一聚酰亚胺膜，另一互连和另外的聚酰亚胺膜; 然后取出晶片和铜膜。 根据本发明，在利用半导体集成电路器件的制造技术的情况下，使用具有以上述方式形成的探针的探测器（薄膜探针）进行探针测试时，可以防止探测器的破损， 待测试的晶圆。

公开(公告)号：US20080160657A1

公开(公告)日：2008-07-03

申请号：US11958369

申请日：2007-12-17

申请人： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

发明人： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

IPC分类号： H01L21/66 ,  H01L21/308

CPC分类号： G01R3/00 ,  G01R1/07342

摘要： A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.

摘要翻译： 通过选择性地在晶片的主表面上沉积在要形成金属膜的区域中的铜膜和当探针卡是在粘合环外部时将在粘合环外部的区域，制造具有足够高度的探针 制造的 形成金属膜，聚酰亚胺膜，互连，另一聚酰亚胺膜，另一互连和另外的聚酰亚胺膜; 然后取出晶圆和铜膜。 根据本发明，在利用半导体集成电路器件的制造技术的情况下，使用具有以上述方式形成的探针的探测器（薄膜探针）进行探针测试时，可以防止探测器的破损， 待测试的晶圆。

公开(公告)号：US08062911B2

公开(公告)日：2011-11-22

申请号：US11958369

申请日：2007-12-17

申请人： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

发明人： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G01R3/00 ,  G01R1/07342

摘要： A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.

摘要翻译： 通过选择性地在晶片的主表面上沉积在要形成金属膜的区域中的铜膜和当探针卡是在粘合环外部时将在粘合环外部的区域，制造具有足够高度的探针 制造的 形成金属膜，聚酰亚胺膜，互连，另一聚酰亚胺膜，另一互连和另外的聚酰亚胺膜; 然后取出晶片和铜膜。 根据本发明，在利用半导体集成电路器件的制造技术的情况下，使用具有以上述方式形成的探针的探测器（薄膜探针）进行探针测试时，可以防止探测器的破损， 待测试的晶圆。

公开(公告)号：US08308887B2

公开(公告)日：2012-11-13

申请号：US13182465

申请日：2011-07-14

申请人： Kazuhiro Isebo ,  Norio Sakai ,  Kenji Kawakami ,  Nobuaki Ogawa

发明人： Kazuhiro Isebo ,  Norio Sakai ,  Kenji Kawakami ,  Nobuaki Ogawa

IPC分类号： B44C1/17 ,  B44C1/165 ,  C03B29/00 ,  B29C65/00 ,  B23P19/00

CPC分类号： H05K3/4061 ,  G03G15/224 ,  G03G15/225 ,  G03G15/6585 ,  G03G15/6591 ,  H05K1/0306 ,  H05K3/1266 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2203/0143 ,  H05K2203/0156 ,  H05K2203/0517 ,  H05K2203/1189 ,  H05K2203/1545 ,  Y10T29/5313 ,  Y10T29/5317 ,  Y10T156/10 ,  Y10T156/109

摘要： A via hole forming method and a multilayered board manufacturing method improve manufacturing yield by reducing the required processes. The via hole forming method includes a first step of forming a toner image by attaching toner particles, containing a conductive material and having a protruding portion, onto the surface of a first photosensitive member so that the protruding portion is directed to the outside; and a second step of opposing the surface of the first photosensitive member to one principal surface of a green sheet containing an insulating material and transferring the toner image to the one principal surface of the green sheet so that the protruding portions of the toner particles protrude into the green sheet so as to reach the other principal surface of the green sheet and the toner particles are buried in the green sheet. The via holes are formed using an electrophotographic printing method.

摘要翻译： 通孔形成方法和多层板制造方法通过减少所需的工艺来提高制造成品率。 通孔形成方法包括：第一步骤，通过将包含导电材料并具有突出部分的调色剂颗粒附着到第一感光构件的表面上以使得突出部分被引导到外部来形成调色剂图像; 以及将第一感光构件的表面相对于包含绝缘材料的生片的一个主表面并将调色剂图像转印到生片的一个主表面的第二步骤，使得调色剂颗粒的突出部分突出到 生片从而到达生片的另一个主表面和调色剂颗粒被埋在生片中。 通孔使用电子照相印刷法形成。

公开(公告)号：US20060014504A1

公开(公告)日：2006-01-19

申请号：US10979114

申请日：2004-11-03

申请人： Masayoshi Ono ,  Kenji Kawakami

发明人： Masayoshi Ono ,  Kenji Kawakami

IPC分类号： H04B1/26

CPC分类号： H03D7/12

摘要： Provided is a pulse modulation circuit that improves the on/off operation and improves the on/off ratio of an output power of the entire pulse modulation circuit in the switching operation. The pulse modulation circuit inputs a local oscillation wave and a DC pulse signal, mixes a second harmonic wave of the local oscillation wave with the DC pulse signal, and outputs an RF pulse signal. The pulse modulation circuit includes: a switch that inputs the local oscillation wave and attenuates the local oscillation wave at an off time more than at an on time; and a harmonic mixer that inputs the local oscillation wave affected by the switch and the DC pulse signal, mixes the second harmonic wave of the local oscillation wave with the DC pulse signal, and outputs the RF pulse signal, in which the switch is allowed to conduct the switching operation together with the harmonic mixer according to the DC pulse signal.

摘要翻译： 提供了一种脉冲调制电路，其改善了开/关操作，并且提高了开关操作中整个脉冲调制电路的输出功率的导通/截止比。 脉冲调制电路输入本地振荡波和直流脉冲信号，将本地振荡波的二次谐波与直流脉冲信号混合，并输出RF脉冲信号。 脉冲调制电路包括：开关，其输入本地振荡波，并在相对于接通时间的关闭时间衰减本地振荡波; 以及输入受开关影响的局部振荡波和直流脉冲信号的谐波混频器，将本地振荡波的二次谐波与直流脉冲信号混合，并输出允许开关的RF脉冲信号 根据直流脉冲信号与谐波混频器一起进行开关操作。