公开(公告)号：US06790710B2

公开(公告)日：2004-09-14

申请号：US10062650

申请日：2002-01-31

Applicant: Neil Robert McLellan ,  Chun Ho Fan ,  Edward G. Combs ,  Tsang Kwok Cheung ,  Chow Lap Keung ,  Sadak Thamby Labeeb

Inventor： Neil Robert McLellan ,  Chun Ho Fan ,  Edward G. Combs ,  Tsang Kwok Cheung ,  Chow Lap Keung ,  Sadak Thamby Labeeb

IPC: H01L2144

CPC classification number: H01L21/568 ,  H01L21/566 ,  H01L23/13 ,  H01L23/5389 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: In one aspect, the present invention features a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, applying a strip to the second surface of the substrate, mounting a semiconductor die on the strip, at least a portion of the semiconductor die being disposed inside the cavity, encapsulating in a molding material at least a portion of the first surface of the substrate, and removing the strip from the substrate. In another aspect, the invention features an integrated circuit package including a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, a semiconductor die electrically coupled with the conductive via, at least a portion of the semiconductor die being disposed inside the cavity of the substrate, an encapsulant material encapsulating a portion of the semiconductor die such that at least a portion of a surface of the semiconductor die is exposed.

Abstract translation: 一方面，本发明的特征在于一种制造集成电路封装的方法，该方法包括提供具有第一表面，与第一表面相对的第二表面的衬底，在第一和第二表面之间穿过衬底的腔，以及延伸穿过 所述基板并且将所述基板的所述第一表面与所述基板的所述第二表面电连接，将所述条带施加到所述基板的所述第二表面，将半导体管芯安装在所述条上，所述半导体管芯的至少一部分设置在所述基板的内部 空腔，将基材的第一表面的至少一部分封装在模制材料中，并从基材上去除带材。 在另一方面，本发明的特征在于集成电路封装，其包括具有第一表面，与第一表面相对的第二表面的衬底，穿过第一和第二表面之间的衬底的腔，以及延伸穿过衬底的导电通孔， 所述基板的第一表面具有所述基板的第二表面，半导体管芯与所述导电通孔电耦合，所述半导体管芯的至少一部分设置在所述基板的空腔内，封装材料封装所述半导体管芯的一部分 使得半导体管芯的表面的至少一部分被暴露。

公开(公告)号：US08538593B2

公开(公告)日：2013-09-17

申请号：US12830028

申请日：2010-07-02

Applicant: David Sun ,  Kwok Cheung ,  Kenneth Chung ,  Tory McKeag

Inventor： David Sun ,  Kwok Cheung ,  Kenneth Chung ,  Tory McKeag

IPC: G05D11/00

CPC classification number: G05B13/02 ,  H02J3/00 ,  H02J2003/003 ,  Y04S10/54

Abstract: A method is provided for merging different load forecasts for power grid centers. Area load forecasts are accepted from load forecast engines. A relational database saves load forecast engine data. A comprehensive operating plan integrates individual load forecasts into a composite load forecast to present a comprehensive, synchronized and harmonized load forecast.

Abstract translation: 提供了一种用于合并电网中心不同负载预测的方法。 负荷预测引擎接受面积负荷预测。 关系数据库可以保存负载预测引擎数据。 综合运营计划将单个负载预测整合到复合负载预测中，以呈现全面，同步和协调的负载预测。

公开(公告)号：US08330270B1

公开(公告)日：2012-12-11

申请号：US11008593

申请日：2004-12-09

Applicant: Geraldine Tsui Yee Lin ,  Walter de Munnik ,  Kin Pui Kwan ,  Wing Him Lau ,  Kwok Cheung Tsang ,  Chun Ho Fan ,  Neil McLellan

Inventor： Geraldine Tsui Yee Lin ,  Walter de Munnik ,  Kin Pui Kwan ,  Wing Him Lau ,  Kwok Cheung Tsang ,  Chun Ho Fan ,  Neil McLellan

IPC: H01L23/495 ,  H01L23/04 ,  H01L23/34

CPC classification number: H01L21/561 ,  H01L21/4828 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An integrated circuit package having a selectively etched leadframe strip defining a die attach pad and a plurality of contact pads, at least one side of the die attach pad having a plurality of spaced apart pad portions; a semiconductor die mounted to the die attach pad and wires bonding the semiconductor die to respective ones of the contact pads; a first surface of the leadframe strip, including the semiconductor die and wire bonds, encapsulated in a molding material such that at least one surface of the leadframe strip is exposed, and wherein solder paste is disposed on said contact pads and said at least one side of said die attach pad.

Abstract translation: 一种集成电路封装，其具有限定管芯附接焊盘和多个接触焊盘的选择性蚀刻的引线框条，所述管芯附接焊盘的至少一侧具有多个间隔开的焊盘部分; 安装到管芯附接焊盘的半导体管芯和将半导体管芯接合到相应的接触焊盘的引线; 引线框带的第一表面，包括半导体管芯和引线接合，封装在模制材料中，使得引线框架条的至少一个表面被暴露，并且其中焊膏设置在所述接触焊盘和所述至少一个侧面上 的所述管芯附接垫。

公开(公告)号：US20110284495A1

公开(公告)日：2011-11-24

申请号：US11916242

申请日：2007-09-20

Applicant: Tung Lok Li ,  Kwok Cheung Tsang ,  Kin Pui Kwan

Inventor： Tung Lok Li ,  Kwok Cheung Tsang ,  Kin Pui Kwan

IPC: H05K13/00

CPC classification number: H01L23/49548 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48639 ,  H01L2224/48655 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Various structures and fabrication methods for leadless plastic chip carrier (QFN) packages which utilize carriers in strip format, wherein the leads (or terminals) are formed to be electrically isolated from one another within each unit and in which the units are formed to be electrically isolated from one another within the strip using chemical etching techniques.

Abstract translation: 用于以带状形式使用载体的无铅塑料芯片载体（QFN）封装的各种结构和制造方法，其中引线（或端子）形成为在每个单元内彼此电绝缘，并且其中单元形成为电 使用化学蚀刻技术在条带内彼此隔离。

公开(公告)号：US20110233206A1

公开(公告)日：2011-09-29

申请号：US12730010

申请日：2010-03-23

Applicant: Cheng Chi Yeung ,  Wai Kwok Cheung

Inventor： Cheng Chi Yeung ,  Wai Kwok Cheung

IPC: B65D6/22

CPC classification number: F16B12/26 ,  B42F7/12 ,  B42F7/145

Abstract: A storage unit having a first sheet having a female connection member defining an opening, and a second sheet having a male connection member. The male connection member can have a neck portion dimensioned to be received in the opening, and can have a retaining portion that is wider than the opening and configured to couple the male and female connection members together. The retaining portion can have a concave edge opposite from the neck portion.

Abstract translation: 一种具有第一片的存储单元，其具有限定开口的阴连接构件和具有阳连接构件的第二片。 阳连接构件可以具有尺寸设计成容纳在开口中的颈部，并且可以具有比开口更宽的保持部分，并且构造成将阳连接构件和阴连接构件联接在一起。 保持部分可以具有与颈部相对的凹形边缘。

公开(公告)号：US20110035071A1

公开(公告)日：2011-02-10

申请号：US12830038

申请日：2010-07-02

Applicant: David Sun ,  Kwok Cheung ,  Kenneth Chung ,  Tory Mckeag

Inventor： David Sun ,  Kwok Cheung ,  Kenneth Chung ,  Tory Mckeag

IPC: G06F1/26

CPC classification number: H02J3/14 ,  G05B15/02 ,  H02J3/00

Abstract: A system tool merges different load forecasts for power grid centers. A plurality of load forecast engines are coupled to a load forecast interface and a relational data base that saves load forecast engine data as an input through the load forecast interface. A comprehensive operating plan is coupled to the load forecast engines and the relational database. The comprehensive operating plan is configured to integrate individual load forecasts into a composite load forecast to present a comprehensive, synchronized and harmonized load forecast. A program interface provides access to the composite load forecasting schedule.

Abstract translation: 系统工具合并了电网中心的不同负载预测。 多个负载预测引擎耦合到负载预测接口和关系数据库，其通过负载预测接口将负载预测引擎数据作为输入节省。 一个全面的运营计划与负载预测引擎和关系数据库相结合。 综合运营计划被配置为将单个负载预测整合到复合负载预测中，以呈现全面，同步和协调的负载预测。 程序界面提供对复合负载预测计划的访问。

公开(公告)号：US20110029147A1

公开(公告)日：2011-02-03

申请号：US12830019

申请日：2010-07-02

Applicant: David Sun ,  Kwok Cheung ,  Xing Wang ,  But-Chung Chiu ,  Ying Xiao

Inventor： David Sun ,  Kwok Cheung ,  Xing Wang ,  But-Chung Chiu ,  Ying Xiao

IPC: G06F1/26

CPC classification number: H02J3/00 ,  G05B15/02 ,  G06Q10/06 ,  G06Q50/06 ,  Y04S10/54

Abstract: A method is provided that enables dispatchers in power grid control centers to manage changes by applying multi-interval dispatch. A multi-stage resource scheduling engine and a comprehensive operating plan are used. Multiple system parameter scenarios are coordinated.

Abstract translation: 提供了一种方法，使得电网控制中心的调度员能够通过应用多间隔调度来管理变更。 使用多阶段资源调度引擎和综合运行计划。 协调多个系统参数场景。

公开(公告)号：US20100202165A1

公开(公告)日：2010-08-12

申请号：US12678690

申请日：2007-09-28

Applicant: Junjie Zheng ,  Jun Zheng ,  Andrew Kwok-Cheung Lee ,  John William Kesterson ,  Allan Ming-Lun Lin ,  Hien Huu Bui ,  Carrie Seim ,  Yong Li

Inventor： Junjie Zheng ,  Jun Zheng ,  Andrew Kwok-Cheung Lee ,  John William Kesterson ,  Allan Ming-Lun Lin ,  Hien Huu Bui ,  Carrie Seim ,  Yong Li

IPC: H02M3/335

CPC classification number: H02M3/33507 ,  H02M2001/0032 ,  H03K17/163 ,  H03K17/166 ,  Y02B70/16

Abstract: A switching power converter comprises a transformer (110), a switch (108) coupled to the transformer (110), and a switch controller (200) coupled to the switch (108) for generating a switch drive signal (207) to turn on or off the switch (108). The drive current of the switch drive signal (207) is adjusted dynamically according to line or load conditions within a switching cycle and/or over a plurality of switching cycles. The magnitude of the drive current can be dynamically adjusted within a switching cycle and/or over a plurality of switching cycles, in addition to the pulse widths or pulse frequencies of the drive current.

Abstract translation: 开关电源转换器包括变压器（110），耦合到变压器（110）的开关（108）和耦合到开关（108）的开关控制器（200），用于产生开关驱动信号（207）以导通 或关闭开关（108）。 开关驱动信号（207）的驱动电流根据开关周期内和/或多个开关周期中的线路或负载条件动态地调整。 除了驱动电流的脉冲宽度或脉冲频率之外，驱动电流的大小可以在开关周期内和/或多个开关周期内动态地调节。

公开(公告)号：US06989294B1

公开(公告)日：2006-01-24

申请号：US10353241

申请日：2003-01-28

Applicant: Neil McLellan ,  Chun Ho Fan ,  Kwok Cheung Tsang ,  Kin Pui Kwan ,  Wing Him Lau

Inventor： Neil McLellan ,  Chun Ho Fan ,  Kwok Cheung Tsang ,  Kin Pui Kwan ,  Wing Him Lau

IPC: H01L21/48

CPC classification number: H01L21/568 ,  H01L21/4832 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H05K1/185 ,  H05K1/187 ,  H05K3/205 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.

公开(公告)号：US06964918B1

公开(公告)日：2005-11-15

申请号：US10757499

申请日：2004-01-15

Applicant: Chun Ho Fan ,  Kwok Cheung Tsang

Inventor： Chun Ho Fan ,  Kwok Cheung Tsang

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/68 ,  H01L23/31 ,  H05K1/18 ,  H05K3/20

CPC classification number: H01L21/568 ,  H01L21/4832 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H05K1/185 ,  H05K1/187 ,  H05K3/205 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A process for fabricating an integrated circuit package includes establishing a plating mask on a first surface of a metal carrier. The plating mask defines a plurality of components including a die attach pad, at least one row of contact pads and at least one additional electronic component. A plurality of metallic layers are deposited on exposed portions of the first surface of the metal carrier. The plating mask is stripped from the metal carrier, leaving the plurality of metallic layers in the form of the plurality of components. A semiconductor die is mounted to die attach pad and pads of the semiconductor die are electrically connected to ones of the contact pads and to the additional electronic component. The first surface of the metal carrier is overmolded to encapsulate the plurality of components and the semiconductor die and the metal carrier is etched away.

Abstract translation: 一种用于制造集成电路封装的方法，包括在金属载体的第一表面上建立电镀掩模。 电镀掩模限定多个部件，包括管芯附接焊盘，至少一排接触焊盘和至少一个附加电子部件。 多个金属层沉积在金属载体的第一表面的暴露部分上。 电镀掩模从金属载体剥离，留下多个金属层以多个部件的形式。 半导体管芯安装到管芯附着焊盘，并且半导体管芯的焊盘电连接到接触焊盘和附加电子部件中的一个。 金属载体的第一表面被包覆成型以封装多个部件，半导体管芯和金属载体被蚀刻掉。