公开(公告)号：US20240153853A1

公开(公告)日：2024-05-09

申请号：US18389651

申请日：2023-12-19

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Nazila Dadvand ,  Bernardo Gallegos

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/49582 ,  H01L21/4825 ,  H01L21/4835 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/562 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/48655 ,  H01L2224/48739 ,  H01L2224/48755 ,  H01L2224/48839 ,  H01L2224/48855 ,  H01L2224/85205 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/15747 ,  H01L2924/35121

摘要： A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.

公开(公告)号：US20180166375A1

公开(公告)日：2018-06-14

申请号：US15837476

申请日：2017-12-11

申请人： Infineon Technologies Austria AG

发明人： Matthias Stecher ,  Martin Kotzbauer ,  Julie Mathilde Suzanne Paye ,  Andreas Zankl

IPC分类号： H01L23/498 ,  H01L23/522 ,  H01L23/00

CPC分类号： H01L23/49894 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49822 ,  H01L23/5222 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/03464 ,  H01L2224/03831 ,  H01L2224/03848 ,  H01L2224/039 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/49171 ,  H01L2224/85375 ,  H01L2924/10253 ,  H01L2924/181 ,  H04L25/0266 ,  H01L2924/01015 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/013 ,  H01L2924/01042 ,  H01L2924/00012 ,  H01L2924/20752 ,  H01L2924/20753

摘要： In an embodiment, a semiconductor device includes a galvanically isolated signal transfer coupler having a contact pad. The contact pad includes a metallic base layer, a metallic diffusion barrier layer arranged on the metallic base layer, and a metallic wire bondable layer arranged on the metallic diffusion barrier layer. The metallic diffusion barrier layer includes a first portion and a second portion. The first portion has a first surface and a second surface opposing the first surface. The first surface has a curved surface at the periphery. The first portion extends in a transverse plane and has a width. The second portion protrudes from the second surface intermediate the width of the first portion.

公开(公告)号：US20180047709A1

公开(公告)日：2018-02-15

申请号：US15793325

申请日：2017-10-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Chung-Shi Liu ,  Ming-Da Cheng

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00 ,  H01L25/10

CPC分类号： H01L25/0657 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/038 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05693 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/1184 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/1358 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48693 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48793 ,  H01L2224/48811 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48893 ,  H01L2224/73204 ,  H01L2224/81009 ,  H01L2224/81026 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/01006

摘要： Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

公开(公告)号：US09887668B2

公开(公告)日：2018-02-06

申请号：US15259995

申请日：2016-09-08

申请人： Skyworks Solutions, Inc.

发明人： Peter J. Zampardi, Jr. ,  Hsiang-Chih Sun ,  Sandra Louise Petty-Weeks ,  Guohao Zhang ,  Hardik Bhupendra Modi

IPC分类号： H03F3/14 ,  H03F1/02 ,  H03F3/19 ,  H03F3/21 ,  H03F3/213 ,  H03F3/195 ,  H03F3/24 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L29/36 ,  H01L29/66 ,  H01L29/737 ,  H01L29/812 ,  H01L29/08 ,  H01L29/205 ,  H01L21/8252 ,  H01L27/06 ,  H01L23/498 ,  H01L23/50 ,  H03F3/60 ,  H01L29/20 ,  H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/8249 ,  H01L21/66 ,  H01L23/31 ,  H01L21/768 ,  H03F3/187 ,  H03F3/347 ,  H03F1/56 ,  H01L29/8605 ,  H01L27/092 ,  H03F3/45 ,  H01L29/06 ,  H01L29/10

CPC分类号： H03F1/0205 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/4864 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/8249 ,  H01L21/8252 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/49861 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/522 ,  H01L23/552 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L27/0605 ,  H01L27/0623 ,  H01L27/092 ,  H01L29/0684 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/20 ,  H01L29/205 ,  H01L29/36 ,  H01L29/66242 ,  H01L29/66863 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/812 ,  H01L29/8605 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/665 ,  H01L2223/6655 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48177 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48611 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48811 ,  H01L2224/48816 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49176 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85411 ,  H01L2224/85416 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12033 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H03F1/565 ,  H03F3/187 ,  H03F3/19 ,  H03F3/195 ,  H03F3/21 ,  H03F3/213 ,  H03F3/245 ,  H03F3/347 ,  H03F3/45 ,  H03F3/60 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2200/48 ,  H03F2200/555 ,  H01L2924/00 ,  H01L2924/00014

摘要： One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and an RF transmission line electrically coupled to an output of the power amplifier. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. The RF transmission line includes a nickel layer with a thickness that is less than 0.5 um, a conductive layer under the nickel layer, a palladium layer over the nickel layer, and a gold layer over the palladium layer. Other embodiments of the module are provided along with related methods and components thereof.

公开(公告)号：US09520835B2

公开(公告)日：2016-12-13

申请号：US14686585

申请日：2015-04-14

申请人： Skyworks Solutions, Inc.

发明人： Tin Myint Ko ,  Philip John Lehtola ,  Matthew Thomas Ozalas ,  David Steven Ripley ,  Hongxiao Shao ,  Peter J. Zampardi, Jr.

IPC分类号： H03F3/195 ,  H03F1/02 ,  H03F3/19 ,  H03F3/21 ,  H03F3/24 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L29/36 ,  H01L29/66 ,  H01L29/737 ,  H01L29/812 ,  H01L29/08 ,  H01L29/205 ,  H01L27/06 ,  H01L23/498 ,  H01L23/50 ,  H03F3/60 ,  H03F3/213 ,  H03F3/187 ,  H03F3/347 ,  H03F3/45 ,  H01L29/8605 ,  H01L21/8252 ,  H01L27/092

CPC分类号： H03F1/0205 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/4864 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/8249 ,  H01L21/8252 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/49861 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/522 ,  H01L23/552 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L27/0605 ,  H01L27/0623 ,  H01L27/092 ,  H01L29/0684 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/20 ,  H01L29/205 ,  H01L29/36 ,  H01L29/66242 ,  H01L29/66863 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/812 ,  H01L29/8605 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/665 ,  H01L2223/6655 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48177 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48611 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48811 ,  H01L2224/48816 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49176 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85411 ,  H01L2224/85416 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12033 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H03F1/565 ,  H03F3/187 ,  H03F3/19 ,  H03F3/195 ,  H03F3/21 ,  H03F3/213 ,  H03F3/245 ,  H03F3/347 ,  H03F3/45 ,  H03F3/60 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2200/48 ,  H03F2200/555 ,  H01L2924/00 ,  H01L2924/00014

摘要： One aspect of this disclosure is a power amplifier module that includes a first die including a power amplifier and a passive component, the power amplifier including a bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3×1016 cm−3 at an interface with the base, the collector also having a grading in which doping concentration increases away from the base; and a second die including a bias circuit configured to generate a bias signal based at least partly on an indication of an electrical property of the passive component of the first die and to provide the bias signal to the power amplifier. Other embodiments of the module are provided along with related methods and components thereof.

摘要翻译： 本公开的一个方面是功率放大器模块，其包括具有功率放大器和无源部件的第一管芯，所述功率放大器包括具有集电极的双极晶体管，邻接所述集电极的基极和发射极，所述集电极具有掺杂 在与碱的界面处浓度为至少约3×1016cm-3，集电体也具有掺杂浓度从基底增加的分级; 以及第二管芯，其包括偏置电路，所述偏置电路被配置为至少部分地基于所述第一管芯的无源部件的电特性的指示来产生偏置信号，并将所述偏置信号提供给所述功率放大器。 模块的其他实施例与其相关方法和组件一起提供。

公开(公告)号：US09437478B2

公开(公告)日：2016-09-06

申请号：US14339360

申请日：2014-07-23

申请人： XINTEC INC.

发明人： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen ,  Ho-Yin Yiu

IPC分类号： H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  G06K9/00 ,  H01L23/00 ,  H01L23/525 ,  H01L23/532

CPC分类号： H01L21/76802 ,  G06K9/00053 ,  H01L21/561 ,  H01L21/76877 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.

摘要翻译： 提供了包括芯片的芯片封装。 芯片包括与芯片的上表面相邻的感测区域或器件区域。 感测阵列位于感测区域或设备区域中并且包括多个感测单元。 多个第一开口位于芯片中并且相应地暴露感测单元。 多个导电延伸部分设置在第一开口中并且电连接到感测单元，其中导电延伸部分从第一开口延伸到芯片的上表面上。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US09355975B2

公开(公告)日：2016-05-31

申请号：US14339355

申请日：2014-07-23

申请人： XINTEC INC.

发明人： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen ,  Chi-Chang Liao

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L29/06 ,  H01L23/525 ,  H01L23/532 ,  H01L25/065

CPC分类号： H01L24/05 ,  H01L21/561 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/10523 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3701 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.

摘要翻译： 提供了包括具有上表面，下表面和侧壁的芯片的芯片封装。 芯片包括与上表面相邻的信号焊盘区域。 第一凹部沿着侧壁从上表面向下表面延伸。 至少一个第二凹部从第一凹部的第一底部向下表面延伸。 第一和第二凹部沿着上表面的侧面进一步横向延伸，并且沿着侧面延伸的第一凹部的长度大于沿着侧面延伸的第二凹部的长度。 再分配层电连接到信号焊盘区域并延伸到第二凹槽中。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US09349675B2

公开(公告)日：2016-05-24

申请号：US14961589

申请日：2015-12-07

申请人： Renesas Electronics Corporation

发明人： Yoshiharu Kaneda

IPC分类号： H01L23/495 ,  H01L23/00

CPC分类号： H01L23/49503 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48639 ,  H01L2224/48655 ,  H01L2224/48739 ,  H01L2224/48755 ,  H01L2224/48839 ,  H01L2224/48855 ,  H01L2224/4903 ,  H01L2224/49505 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/20752 ,  H01L2924/2076 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01046

摘要： A method of manufacturing a semiconductor device includes preparing a lead frame provided with a die pad having an upper surface and a plurality of leads being arranged so as to be aligned on a side of the die pad and each including a wire joint part at a distal end on the side of the die pad, after the preparing the lead frame, mounting a semiconductor chip having a main surface and a plurality of electrode pads formed on the main surface, on the upper surface of the die pad, and after the mounting the semiconductor chip, electrically connecting a first electrode pad among the plurality of electrode pads of the semiconductor chip and a first lead among the plurality of leads to each other via a first wire.

摘要翻译： 一种半导体器件的制造方法，包括：准备具有上表面的芯片焊盘的引线框架，并且多个引线被配置为在芯片焊盘的一侧对准，并且每个引线框架包括在远端 在芯片焊盘的一侧端部，在准备引线框架之后，在芯片焊盘的上表面上安装具有形成在主表面上的主表面和多个电极焊盘的半导体芯片，并且在安装之后 将所述半导体芯片的多个电极焊盘中的第一电极焊盘与所述多个引线中的第一引线经由第一焊丝电连接。

公开(公告)号：US20160086875A1

公开(公告)日：2016-03-24

申请号：US14961589

申请日：2015-12-07

申请人： Renesas Electronics Corporation

发明人： YOSHIHARU KANEDA

IPC分类号： H01L23/495 ,  H01L23/00

CPC分类号： H01L23/49503 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48639 ,  H01L2224/48655 ,  H01L2224/48739 ,  H01L2224/48755 ,  H01L2224/48839 ,  H01L2224/48855 ,  H01L2224/4903 ,  H01L2224/49505 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/20752 ,  H01L2924/2076 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01046

摘要： A method of manufacturing a semiconductor device includes preparing a lead frame provided with a die pad having an upper surface and a plurality of leads being arranged so as to be aligned on a side of the die pad and each including a wire joint part at a distal end on the side of the die pad, after the preparing the lead frame, mounting a semiconductor chip having a main surface and a plurality of electrode pads formed on the main surface, on the upper surface of the die pad, and after the mounting the semiconductor chip, electrically connecting a first electrode pad among the plurality of electrode pads of the semiconductor chip and a first lead among the plurality of leads to each other via a first wire.

摘要翻译： 一种半导体器件的制造方法，包括：准备具有上表面的芯片焊盘的引线框架，并且多个引线被配置为在芯片焊盘的一侧对准，并且每个引线框架包括在远端 在芯片焊盘的一侧端部，在准备引线框架之后，在芯片焊盘的上表面上安装具有形成在主表面上的主表面和多个电极焊盘的半导体芯片，并且在安装之后 将所述半导体芯片的多个电极焊盘中的第一电极焊盘与所述多个引线中的第一引线经由第一焊丝电连接。

公开(公告)号：US09287226B2

公开(公告)日：2016-03-15

申请号：US14538265

申请日：2014-11-11

申请人： Skyworks Solutions, Inc.

发明人： Weimin Sun ,  Peter J. Zampardi, Jr. ,  Hongxiao Shao

IPC分类号： H01L29/00 ,  H01L29/80 ,  H01L23/00 ,  H01L23/64 ,  H01L23/66 ,  H01L23/495 ,  H01L23/498

CPC分类号： H01L24/09 ,  H01L23/4952 ,  H01L23/49838 ,  H01L23/642 ,  H01L23/66 ,  H01L24/03 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L2223/6605 ,  H01L2224/0346 ,  H01L2224/095 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/49111 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/19011 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/45099

摘要： To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to the RF signal output of the RFIC. By placing the on-die passive device in the RF upper signal path, the RF current does not directly pass through the high RF loss plating material of the passive device bonding pad.

摘要翻译： 为了减少与高RF损耗电镀相关的射频（RF）损耗，例如镍/钯/金（Ni / Pd / Au）电镀，诸如电容器，电阻器等的裸片无源器件， 或与电射频集成电路（RFIC）相关联的电感器被放置在相对于RFIC的RF信号输出的RF上信号路径中。 通过将片上无源器件放置在RF上信号路径中，RF电流不直接通过无源器件焊盘的高RF损耗电镀材料。