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    Hermetic seal and reliable bonding structures for 3D applications
    11.
    发明授权
    Hermetic seal and reliable bonding structures for 3D applications 失效
    密封密封和3D应用的可靠结合结构

    公开(公告)号：US07683478B2

    公开(公告)日：2010-03-23

    申请号：US12026776

    申请日：2008-02-06

    Applicant: Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

    Inventor： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

    IPC: H01L23/34

    CPC classification number: H01L25/50 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

    Abstract translation: 一种密封的微电子结构，其提供机械应力耐久性并且包括在多个位置处电连接到半导体结构的至少两个芯片。 每个芯片沿着其周边包括连续的接合材料，以及连接到位于每个芯片的周边内的每个芯片的至少一个支撑柱。 每个支撑柱向外延伸，使得当至少两个芯片彼此定位时，支撑柱彼此配合。 至少两个芯片之间的密封由芯片彼此的重叠关系产生，使得接合材料和支撑柱彼此配合。 因此，当至少两个芯片配合在一起时形成密封，并且导致粘合芯片结构。

    THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS
    12.
    发明申请
    THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS 有权
    用于控制集成电路中静态功耗的三端子开关

    公开(公告)号：US20090315010A1

    公开(公告)日：2009-12-24

    申请号：US12551631

    申请日：2009-09-01

    Applicant: Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    Inventor： Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    IPC: H01L45/00

    CPC classification number: H01L45/1226 ,  H01L27/24 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148

    Abstract: A three-terminal switching device for use in integrated circuit devices, including a phase change material (PCM) disposed in contact between a first terminal and a second terminal; a heating device disposed in direct electrical contact between said second terminal and a third terminal, said heating device positioned proximate said PCM, and configured to switch the conductivity of a transformable portion of said PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate said heater from said PCM material, and said heater from said first terminal.

    Abstract translation: 一种用于集成电路装置的三端开关装置，包括设置在第一端子和第二端子之间的相变材料（PCM）; 加热装置，其设置在所述第二端子和第三端子之间的直接电接触中，所述加热装置位于所述PCM附近，并且被配置为将所述PCM的可变形部分的电导率切换到较低电阻结晶状态和较高电阻无定形状态 ; 以及绝缘层，其被配置为将所述加热器与所述PCM材料电隔离，并且所述加热器从所述第一端子电隔离。

    THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS
    13.
    发明申请
    THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS 有权
    用于控制集成电路中静态功耗的三端子开关

    公开(公告)号：US20080210925A1

    公开(公告)日：2008-09-04

    申请号：US12122969

    申请日：2008-05-19

    Applicant: Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    Inventor： Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    IPC: H01L45/00

    CPC classification number: H01L45/1226 ,  H01L27/24 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148

    Abstract: A switching circuit configured for controlling static power consumption in integrated circuits includes a plurality of three-terminal, phase change material (PCM) switching devices connected between a voltage supply terminal and a corresponding sub-block of integrated circuit logic. Each of the PCM switching devices further includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.

    Abstract translation: 配置成用于控制集成电路中的静态功耗的开关电路包括连接在电压源端子和集成电路逻辑的对应子块之间的多个三端子相变材料（PCM）开关器件。 每个PCM开关装置还包括设置在第一端子和第二端子之间接触的PCM，在第二端子和第三端子之间接触地设置的加热装置，加热装置位于PCM附近，并且被配置为将 PCM的可变形部分的电导率在较低电阻结晶状态和较高电阻无定形状态之间; 以及绝缘层，其被配置为将加热器与所述PCM材料电隔离，并且所述加热器与所述第一端子电隔离。 第一个PCM开关器件的第三个端子耦合到一个设置/复位开关，其余的PCM开关器件的第三个端子以级联配置耦合到相邻PCM开关器件的第二个端子。

    Integrated circuit planarization and fill biasing design method
    15.
    发明授权
    Integrated circuit planarization and fill biasing design method 有权
    集成电路平面化和填充偏置设计方法

    公开(公告)号：US6121078A

    公开(公告)日：2000-09-19

    申请号：US154652

    申请日：1998-09-17

    Applicant: John K. DeBrosse ,  Matthew R. Wordeman

    Inventor： John K. DeBrosse ,  Matthew R. Wordeman

    IPC: H01L21/762 ,  H01L21/82 ,  H01L27/06 ,  H01L21/338

    CPC classification number: H01L21/76224 ,  H01L21/82 ,  H01L27/0629

    Abstract: An isolation and gate planarization method for an integrated circuit chip and chips designed by the method. The method comprises generating a dummy gate conductor (GC) shape and biasing it to the underlying well. The method may further comprise generating an active area (AA) dummy shape underlying the GC dummy shape. Biasing may be to the same voltage as the underlying well, or may be to a different voltage to create a decoupling capacitor. The biasing may be accomplished by implanting a well contact on an active area shape, the contact being N+ over an N-well or P+ over a P-well.

    Abstract translation: 一种用于集成电路芯片和芯片设计的隔离栅极平面化方法。 该方法包括产生虚拟栅极导体（GC）形状并将其偏压到下面的阱。 该方法还可以包括生成下面的GC虚拟形状的有源区（AA）虚拟形状。 偏置可能与下面的阱具有相同的电压，或者可以是不同的电压以产生去耦电容器。 偏置可以通过在有源区域形状上注入阱接触来实现，该触点是通过P阱的N阱或P +上的N +。

    3D inter-stratum connectivity robustness
    16.
    发明授权
    3D inter-stratum connectivity robustness 有权
    3D层间连通性鲁棒性

    公开(公告)号：US08381156B1

    公开(公告)日：2013-02-19

    申请号：US13217381

    申请日：2011-08-25

    Applicant: Michael P. Beakes ,  Shih-Hsien Lo ,  Michael R. Scheuermann ,  Matthew R. Wordeman

    Inventor： Michael P. Beakes ,  Shih-Hsien Lo ,  Michael R. Scheuermann ,  Matthew R. Wordeman

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/40 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.

    Abstract translation: 提供了一种用于验证要组合成3D芯片堆栈的两个或更多个层的层间连通性的方法。 两个或更多个层中的每一个具有包括主动3D元素，机械3D元素和虚拟3D元素的3D元素。 该方法包括相对于至少3D元件在两个或更多个层中的每一个上执行相应的2D布局，以相对于示意图验证，以便当两个或更多个层随后被堆叠到3D元素中时，预先确保在3D元件之间不存在短路 3D芯片堆栈。 该方法还包括检查3D芯片堆叠中每个相邻层之间的层间互连性。

    THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS
    17.
    发明申请
    THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS 有权
    用于控制集成电路中静态功耗的三端子开关

    公开(公告)号：US20120153248A1

    公开(公告)日：2012-06-21

    申请号：US13406096

    申请日：2012-02-27

    Applicant: Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    Inventor： Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    IPC: H01L45/00

    CPC classification number: H01L45/1226 ,  H01L27/24 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148

    Abstract: A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.

    Abstract translation: 开关电路包括连接在电压供给端子和逻辑子块之间的多个三端子PCM开关装置。 每个开关装置包括设置在第一端子和第二端子之间接触的PCM，加热装置，其设置成接触在第二端子和第三端子之间，加热装置位于PCM附近，并且被配置为切换 PCM的可变形部分在较低电阻状态和较高电阻状态之间; 以及绝缘层，其被配置为将加热器与所述PCM材料电隔离，并且所述加热器与所述第一端子电隔离。 第一个PCM开关器件的第三个端子耦合到一个设置/复位开关，其余的PCM开关器件的第三个端子以级联配置耦合到相邻PCM开关器件的第二个端子。

    Three-terminal cascade switch for controlling static power consumption in integrated circuits
    19.
    发明授权
    Three-terminal cascade switch for controlling static power consumption in integrated circuits 有权

    公开(公告)号：US07652279B2

    公开(公告)日：2010-01-26

    申请号：US12122969

    申请日：2008-05-19

    Applicant: Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    Inventor： Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

    IPC: H01L47/00

    CPC classification number: H01L45/1226 ,  H01L27/24 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148

    Abstract: A switching circuit configured for controlling static power consumption in integrated circuits includes a plurality of three-terminal, phase change material (PCM) switching devices connected between a voltage supply terminal and a corresponding sub-block of integrated circuit logic. Each of the PCM switching devices further includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.

    Differential and hierarchical sensing for memory circuits
    20.
    发明授权
    Differential and hierarchical sensing for memory circuits 失效
    存储电路的差分和分层感测

    公开(公告)号：US07286385B2

    公开(公告)日：2007-10-23

    申请号：US11190542

    申请日：2005-07-27

    Applicant: John Edward Barth, Jr. ,  Paul C. Parries ,  William Robert Reohr ,  Matthew R. Wordeman

    Inventor： John Edward Barth, Jr. ,  Paul C. Parries ,  William Robert Reohr ,  Matthew R. Wordeman

    IPC: G11C5/06 ,  G11C8/00

    CPC classification number: G11C7/12 ,  G11C7/02 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/4094

    Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.

    Abstract translation: 存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。 每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。 至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。

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